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Blackfin: fix composev2hi pattern


This is an old patch (from 2007) which has so far only been in our local
tree and never made it back to mainline.  It fixes a bug in the
composev2hi pattern/builtin function; operands were swapped.

Committed as 141311.  A testcase for the problem is on its way along
with the next patch.


Bernd
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Index: ChangeLog
===================================================================
--- ChangeLog	(revision 141310)
+++ ChangeLog	(working copy)
@@ -1,3 +1,9 @@
+2008-10-23  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Jie Zhang  <jie.zhang@analog.com>
+	* config/bfin/bfin.md (composev2hi): Put operands into vector
+	with correct order.
+	
 2008-10-22  Chao-ying Fu  <fu@mips.com>
 
 	* config/mips/mips.opt (msmartmips): Accept -mno-smartmips.
Index: config/bfin/bfin.md
===================================================================
--- config/bfin/bfin.md	(revision 140230)
+++ config/bfin/bfin.md	(working copy)
@@ -2886,16 +2886,16 @@ (define_insn_and_split "composev2hi"
 			 (match_operand:HI 1 "register_operand" "d,d")))]
   ""
   "@
-   %d0 = %h2 << 0%!
+   %d0 = %h1 << 0%!
    #"
   "reload_completed"
   [(set (match_dup 0)
 	(vec_concat:V2HI
 	 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
-	 (match_dup 2)))
+	 (match_dup 1)))
    (set (match_dup 0)
 	(vec_concat:V2HI
-	 (match_dup 1)
+	 (match_dup 2)
 	 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
   ""
   [(set_attr "type" "dsp32")])

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