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In the "stack_protect_set" and "stack_protect_test_si" patterns, the
type attribute should be multi1. This indicates that the first
instruction is in the odd pipeline, which allows slightly better
scheduling of these patterns.

In "stack_protect_test_si", shouldn't the "+r" of the first operand be
"=&r"?  Also, please change "register_operand" to "spu_reg_operand".
Based on the code, it is not necessary now, but it protects us from
possible issues in the future.

I'm a little suspicious of the memory predicates, constraints, and the
hard coded load/store instructions.  How do we know that the memory rtl
will always match the hard coded instructions?

How did you compare the test suite results?  Did you use
contrib/compare_tests?  Or just compare the numbers/statistics printed
at the end?  (Use compare_tests.)


* Stefan Schulze Frielinghaus <> [2008-10-21 07:00]:
> Hi,
> to use the Stack Smashing Protector the frame needs to grow downwards.
> Attached patch accomplishes that for the Cell B.E. SPU architecture.
> Tested against regression suite without any difference in pass/fail
> statistics (except the extra test passes for SSP)..
> OK for mainline?
> (See attached file: spu.patch)
> Mit freundlichen Gruessen / Kind regards
> Stefan Schulze Frielinghaus
> IBM Systems & Technology Group, Systems Software Development
> SW Linux on Cell BE Development & Evaluation
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