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[PATCH, i386]: Do not force arith/logic insn memory operands into registers for ! TARGET_READ_MODIFY


Hello!

Attached patch fixed an oversight with a peephole2 pattern that forces memory operands of arithmetic and logic instructions into registers. This optimisation is relevant only for TARGET_READ_MODIFY targets; this insn constraint was lost during "optimize_insn_for_speed_p ()" conversion.

This problem was spotted while looking at PR target/37823, so there are also some operand predicate fixes for ffs patterns in this patch.

Without TARGET_READ_MODIFY fix, following testcase from the PR:

--cut here--
#include <strings.h>

int
foo(int i, int j)
{
 return i + ffs(j) - 1;
}
--cut here--

generates (-O2 -m32 -march=core2):

foo:
   bsfl    8(%esp), %eax
   movl    $-1, %edx
   cmove    %edx, %eax
   movl    4(%esp), %edx
   addl    %edx, %eax
   ret

With attached patch:

foo:
   bsfl    8(%esp), %eax
   movl    $-1, %edx
   cmove    %edx, %eax
   addl    4(%esp), %eax
   ret

2008-10-18 Uros Bizjak <ubizjak@gmail.com>

   * config/i386/i386.md (unnamed peephole2): Do not force memory
   operands of arith or logical instructions into registers for
   non-TARGET_READ_MODIFY targets.

   (ffs_cmove): Change operand 0 predicate to register_operand.
   Change operand 1 predicate to nonimmediate_operand.
   (ffsdi2): Ditto.
   (*ffs_no_cmove): Change operand 0 predicate to register_operand.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}. Patch is committed to SVN.

Uros.


Index: i386.md
===================================================================
--- i386.md	(revision 141210)
+++ i386.md	(working copy)
@@ -15366,9 +15366,9 @@
 (define_expand "ffs_cmove"
   [(set (match_dup 2) (const_int -1))
    (parallel [(set (reg:CCZ FLAGS_REG)
-		   (compare:CCZ (match_operand:SI 1 "register_operand" "")
+		   (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
 				(const_int 0)))
-	      (set (match_operand:SI 0 "nonimmediate_operand" "")
+	      (set (match_operand:SI 0 "register_operand" "")
 		   (ctz:SI (match_dup 1)))])
    (set (match_dup 0) (if_then_else:SI
 			(eq (reg:CCZ FLAGS_REG) (const_int 0))
@@ -15380,7 +15380,7 @@
   "operands[2] = gen_reg_rtx (SImode);")
 
 (define_insn_and_split "*ffs_no_cmove"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&q"))
    (clobber (reg:CC FLAGS_REG))]
@@ -15416,9 +15416,9 @@
 (define_expand "ffsdi2"
   [(set (match_dup 2) (const_int -1))
    (parallel [(set (reg:CCZ FLAGS_REG)
-		   (compare:CCZ (match_operand:DI 1 "register_operand" "")
+		   (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
 				(const_int 0)))
-	      (set (match_operand:DI 0 "nonimmediate_operand" "")
+	      (set (match_operand:DI 0 "register_operand" "")
 		   (ctz:DI (match_dup 1)))])
    (set (match_dup 0) (if_then_else:DI
 			(eq (reg:CCZ FLAGS_REG) (const_int 0))
@@ -20684,7 +20684,7 @@
                      [(match_dup 0)
                       (match_operand:SI 1 "memory_operand" "")]))
               (clobber (reg:CC FLAGS_REG))])]
-  "optimize_insn_for_speed_p ()"
+  "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
   [(set (match_dup 2) (match_dup 1))
    (parallel [(set (match_dup 0)
                    (match_op_dup 3 [(match_dup 0) (match_dup 2)]))

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