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Re: [PATCH] MIPS function attributes for interrupt handlers


"Fu, Chao-Ying" <fu@mips.com> writes:
> Index: gcc4x/gcc/gcc/config/mips/mips.c
> ===================================================================
> --- gcc4x.orig/gcc/gcc/config/mips/mips.c	2008-10-13 17:29:33.000000000 -0700
> +++ gcc4x/gcc/gcc/config/mips/mips.c	2008-10-13 18:23:06.000000000 -0700
> @@ -8977,6 +9360,127 @@ mips_output_function_prologue (FILE *fil
>       pointer.  This is needed for thunks, since they can use either
>       explicit relocs or assembler macros.  */
>    mips_output_cplocal ();
> +
> +  /* If this is an interrupt function, we need to save that
> +     context first.  We don't want to use the generic
> +     mips_for_each_saved_reg() function because we want to
> +     leave defined values in K0 and K1.  */
> +  if (cfun->machine->frame.has_interrupt_context_p)
> +    {
> +      unsigned int i;
> +      HOST_WIDE_INT step1;
> +      HOST_WIDE_INT offset;
> +      HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
> +
> +      step1 = MIN (tsize, MIPS_MAX_FIRST_STACK_STEP);
> +
> +      /* If this interrupt is using a shadow register set, we need to
> +         get the stack pointer from the previous register set.  */
> +      /* Trumping that concern, at least for the time being, is that we
> +         want the first four instructions of the interrupt handler to be
> +         the same for all handler functions.  This lets there be cache lines
> +         locked to those instructions, lowering the latency.  */
> +      /* if (current_function_type == SRS_CONTEXT_SAVE) */
> +	  fprintf (file, "\trdpgpr\t$sp, $sp\n");

You seems to be using MIPS32r2 instructions in the prologue.  I think this
should be emitted in RTL.

> Index: gcc4x/gcc/gcc/doc/extend.texi
> ===================================================================
> --- gcc4x.orig/gcc/gcc/doc/extend.texi	2008-10-13 17:25:41.000000000 -0700
> +++ gcc4x/gcc/gcc/doc/extend.texi	2008-10-13 17:33:02.000000000 -0700
> @@ -2386,6 +2386,56 @@ Permissible values for this parameter ar
>  On ARMv7-M the interrupt type is ignored, and the attribute means the function
>  may be called with a word aligned stack pointer.
>  
> +Note, for the MIPS, you must specify the kind of interrupt to be handled by
> +adding a parameter to the interrupt attribute like this:
> +
> +@smallexample
> +void f () __attribute__ ((interrupt (single)));
> +@end smallexample
> +
> +The funciton f is a single interrupt handler that deals with all interrupts.
> +
> +@smallexample
> +void g () __attribute__ ((interrupt (ipl6)));
> +@end smallexample
> +
> +The funciton g is an interrupt handler that handles interrupts at the
> +priority level of 6.
> +
> +Permissible values for this parameter are: single, ipl0, ipl1, ipl2, ipl3,
> +ipl4, ipl5, ipl6, ipl7.  If ipl7 is used, a shadow register set is
> +used for context switch to reduce interrupt latency.  For parameters other
> +than ipl7, normal load and store instructions are used for context switch.
> +Note that MIPS interrupt handlers assume the stack pointer is valid at all
> +time.

It seems that ipl7 implies two things: use the shadow register set and that
all interrupts should remain masked.  It seems the second can be useful even
if the processor does not support shadow registers.  One idea would be to
split the two and make them explicit (e.g. use_shadow_register_set and
keep_interrupts_masked attributes).

> +@item at_vector
> +@cindex install interrupt handler at the address of exception vector on MIPS
> +Using this attribute on MIPS indicates that the specific interrupt handler
> +should be located at the address of the exception vector (from 0 to 63).
> +
> +@smallexample
> +void f ()  __attribute__ ((interrupt(single))) __attribute__((at_vector (20)));
> +@end smallexample
> +
> +The single interrupt handler f is installed at the exception vectors 20
> +which section name is ".vector_20".

I think we shouldn't suggest here that we install this function at a certain
address but be clear that all this does is to put the function into a named
section.

Adam


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