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Re: [PATCH, i386]: Add support for CPUID 4 in driver-i386.c

Andi Kleen wrote:

This patch is loosely based on Andi's patch to use CPUID function 4 to describe Intel caches. In addition to parsing CPUID function 4 values, attached patch updates CPUID 2 table to the latest known CPUID documentation, it fixes Xeon MP CPUID fn 2 problems and handles number of times to execute CPUID fn 2 instruction to obtain complete cache hierarchy description.

I suspect the CPUID 2 table update is not really needed, because
most CPUs now can describe themselves using CPUID 4.

True, but where do we want to cut the table? IMO, it is better to follow the documentation and provide complete table with all documented fixups to avoid surprises in the future.

The xeon_mp variable is quite misnamed because there are lots of quite
different SKUs calling themselves that. Also it wouldn't surprise
me if that CPU already had CPUID 4, so the hack is likely not needed.

This is how the fixup is referred in the doc. Please look at page 30 of CPUID ApplicationNote 485.

+ for (i = 24; i >= 0; i -= 8)
+ switch ((reg >> i) & 0xff)
+ {
+ case 0x0a:

As a personal nit if you're going to redo this anyways then
a lookup table would be much shorter than code.

Sparse 256-slot table that deals with two (and perhaps someday three) different cache descriptors, indexed by a char selector? I don't think so, but the patch that further cleans this messy stuff is always welcome.

+ case CACHE_END:
+ return;
+ case CACHE_DATA:
+ {
+ switch ((eax >> 5) & 0x07)
+ {
+ case 1:
+ cache = level1;
+ break;
+ case 2:
+ cache = level2;
+ break;
+ default:
+ cache = NULL;

That seems like a weird value for a enum

Huh? We are talking about

enum cache_type


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