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Re: Support Xilinx PowerPC single-precision FPU

David Edelsohn wrote:

Your change to fix_truncsfsi2 references gen_xil_fix_truncsfsi2,
but no xil_fix_truncsfsi2 pattern is defined in your patches.

xil_fix_truncsfsi2 as well as a couple other patterns are not being submitted, at least for the time being, since Xilinx has redefined 'fctiwz' instruction to operate on SF values.

I meant to exclude the modifications to the fix_truncsfsi2
pattern as well.  I believe that the support for Xilinx's 'fctiwz'
instruction can be reworked so that it doesn't need any changes to

The attached patch reverts these changes.

Michael Eager
1960 Park Blvd., Palo Alto, CA 94306  650-325-8077
---	2008-10-10 12:43:08.000000000 -0700
+++	2008-10-10 12:44:06.000000000 -0700
@@ -5862,18 +5862,8 @@
 	     (clobber (match_dup 2))
 	     (clobber (match_dup 3))
 	     (clobber (match_dup 4))])]
-  "
-    {
-      operands[2] = gen_reg_rtx (SFmode);
-      operands[3] = assign_stack_temp (SFmode, GET_MODE_SIZE (SFmode), 0);
-      operands[4] = gen_rtx_MEM (SImode, XEXP (operands[3], 0));
-      emit_insn (gen_xil_fix_truncsfsi2(operands[0], operands[1], operands[2], operands[3], operands[4]));
-      DONE;
-    }
+  "")
 ; For each of these conversions, there is a define_expand, a define_insn
 ; with a '#' template, and a define_split (with C code).  The idea is

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