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Re: [wwwdocs] Add entries for MIPS64r2 and Octeon in changes.html
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Adam Nemet <anemet at caviumnetworks dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 23 Sep 2008 20:09:52 +0100
- Subject: Re: [wwwdocs] Add entries for MIPS64r2 and Octeon in changes.html
- References: <18648.7867.647271.937962@foo.home>
Adam Nemet <anemet@caviumnetworks.com> writes:
> Index: changes.html
> ===================================================================
> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.4/changes.html,v
> retrieving revision 1.31
> diff -u -r1.31 changes.html
> --- changes.html 19 Sep 2008 23:06:49 -0000 1.31
> +++ changes.html 22 Sep 2008 22:23:54 -0000
> @@ -348,6 +348,12 @@
> <li>GCC can now work around the side effects of speculative execution
> on R10K processors. Please see the documentation of the
> <code>-mr10k-cache-barrier</code> option for details.</li>
> + <li>Support for the MIPS64 Release 2 instruction set has been added. The
> + option <code>-march=mips64r2</code> enables generation of these
> + instructions.</li>
> + <li>GCC now supports Cavium Networks' Octeon processor. This support is
> + available through the <code>-march=octeon</code> and
> + <code>-mtune=octeon</code> options.</li>
> </ul>
>
> <h3 id="picochip">picochip</h3>
OK, thanks.
Richard