This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH] Fix middle-end/36444, ICE gen_lowpart_general with -O1 with vector registers
- From: "Richard Guenther" <richard dot guenther at gmail dot com>
- To: "Andrew Pinski" <Andrew_Pinski at playstation dot sony dot com>
- Cc: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 30 Aug 2008 15:40:05 +0200
- Subject: Re: [PATCH] Fix middle-end/36444, ICE gen_lowpart_general with -O1 with vector registers
- References: <de8d50360808291455o184ee114g3bed0d6c1b91f906@mail.gmail.com>
On Fri, Aug 29, 2008 at 11:55 PM, Andrew Pinski
<Andrew_Pinski@playstation.sony.com> wrote:
> Hi,
> The problem here is that extract_bit_field_1 would try to get a
> different vector mode to do the extraction if the we had originally a
> VIEW_CONVERT_EXPR (a subreg on the RTL level) to a different mode. So
> we would get the wrong mode as we would pick a mode which was no where
> near the original mode. That is we would pick V8SI instead of V8QI as
> the check for the mode was checking the number of elements instead of
> mode sizes. This patch fixes the problem by checking the mode sizes
> instead of the number of elements.
>
> OK? Bootstrapped and tested on powerpc64-linux-gnu and i386-darwin
> with no regressions.
Ok.
Thanks,
Richard.
> Thanks,
> Andrew Pinski
>
> ChangeLog:
>
> * expmed.c (extract_bit_field_1): Check the mode size to make sure the
> vector modes have the same size.
>
> * g++.dg/torture/pr36444.C: New testcase.
> * gcc.c-torture/compile/vector-4.c: New testcase.
>