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Re: mips64 xlr processor support
- From: Sandip Matte <sandip at rmicorp dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>, gcc-patches at gcc dot gnu dot org
- Date: Thu, 05 Jun 2008 18:15:24 +0530
- Subject: Re: mips64 xlr processor support
- References: <483C0968.9060502@rmicorp.com> <87hccj4m4e.fsf@firetop.home>
Hi Richard,
I have updated the xlr patch with all the comments. RMI
has signed a copyright agreement with FSF. Also, As per David's
comment, new xlr target is not added.
Please review the patch and let me know the comments.
Thanks,
Sandip
Richard Sandiford wrote:
Hi Sandip,
Sandip Matte <sandip@rmicorp.com> writes:
This patch adds support for RMI Corp's mips64 xlr processor.
New option -march=xlr and -mtune=xlr are added for xlr
processor. Tested mips64-unknown-linux-gnu with -march=xlr and
-mtune=xlr.
Thanks for the patch. It generally looks good. You need to submit a
patch against SVN mainline first though; this one is against 4.2, and
some of the insn "type"s have been split since then.
You need to document the new -march option in doc/invoke.texi.
(Please keep the list there alphabetically sorted.)
The formatting of the patch isn't very self-consistent,
but I can fix that up before applying.
Most important of all though:
+;; Software Code Disclaimer
+;; xlr.md Machine Description for the RMI XLR Microprocessor
+;; Copyright © 2008 Raza Microelectronics, Inc. "RMI")
+;;
+;; This program is free software. You may use it, redistribute it
+;; and/or modify it under the terms of the GNU General Public License
+;; as published by the Free Software Foundation; either version two
+;; of the License or (at your option) any later version.
+;;
+;; This program is distributed in the hope that you will find it
+;; useful. Notwithstanding the foregoing, you understand and agree
+;; that this program is provided by RMI "as is," and without any
+;; warranties, whether express, implied or statutory, including without
+;; limitation any implied warranty of non-infringement, merchantability
+;; or fitness for a particular purpose. In no event will RMI be liable
+;; for any loss of data, lost profits, cost of procurement of substitute
+;; technology or services or for any direct, indirect, incidental,
+;; consequential or special damages arising from the use of this program,
+;; however caused. Your unconditional agreement to these terms and
+;; conditions is an express condition to, and shall be deemed to occur
+;; upon, your use, redistribution and/or modification of this program.
+;;
+;; See the GNU General Public License for more details.
...we can only accept the patch if RMI assigns the copyright to
the Free Software Foundation. Has RMI already signed a copyright
agreement with the FSF? If not, you need to do that first.
If so, you need to change the copyright notice to match the
usual FSF one; see other config/mips files for details.
Richard
--
The bulk of the world’s knowledge is an imaginary construction. -Helen Keller
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 136391)
+++ gcc/doc/invoke.texi (working copy)
@@ -11987,7 +11987,8 @@
@samp{sb1},
@samp{sr71000},
@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
-@samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
+@samp{vr5000}, @samp{vr5400}, @samp{vr5500}
+and @samp{xlr}.
The special value @samp{from-abi} selects the
most compatible architecture for the selected ABI (that is,
@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
Index: gcc/config/mips/xlr.md
===================================================================
--- gcc/config/mips/xlr.md (revision 0)
+++ gcc/config/mips/xlr.md (revision 0)
@@ -0,0 +1,91 @@
+;; DFA-based pipeline description for the XLR.
+;; Copyright (C) 2008 Free Software Foundation, Inc.
+;;
+;; xlr.md Machine Description for the RMI XLR Microprocessor
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "xlr_main,xlr_muldiv")
+
+;; definitions for xlr_main automaton
+(define_cpu_unit "xlr_main_pipe" "xlr_main")
+
+(define_insn_reservation "ir_xlr_alu_slt" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "slt"))
+ "xlr_main_pipe")
+
+;; integer arithmetic instructions
+(define_insn_reservation "ir_xlr_alu" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "arith,shift,clz,const,unknown,multi,nop,trap"))
+ "xlr_main_pipe")
+
+;; integer arithmetic instructions
+(define_insn_reservation "ir_xlr_condmove" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "condmove"))
+ "xlr_main_pipe")
+
+;; load/store instructions
+(define_insn_reservation "ir_xlr_load" 4
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "load"))
+ "xlr_main_pipe")
+
+(define_insn_reservation "ir_xlr_store" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "store"))
+ "xlr_main_pipe")
+
+(define_insn_reservation "ir_xlr_prefetch_x" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "prefetch,prefetchx"))
+ "xlr_main_pipe")
+
+;; Do we Need to schedule branch? What are really scheduling???
+;; branch instructions -Use branch misprediction latency
+(define_insn_reservation "ir_xlr_branch" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "branch,jump,call"))
+ "xlr_main_pipe")
+
+;; coprocessor move instructions
+(define_insn_reservation "ir_xlr_xfer" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "mtc,mfc"))
+ "xlr_main_pipe")
+
+(define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer")
+
+;; definitions for the xlr_muldiv automaton
+(define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv")
+
+(define_insn_reservation "ir_xlr_imul" 8
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "imul,imul3,imadd"))
+ "xlr_main_pipe,xlr_imuldiv_nopipe*6")
+
+(define_insn_reservation "ir_xlr_div" 68
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "idiv"))
+ "xlr_main_pipe,xlr_imuldiv_nopipe*67")
+
+(define_insn_reservation "xlr_hilo" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "mfhilo,mthilo"))
+ "xlr_imuldiv_nopipe")
+
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md (revision 136391)
+++ gcc/config/mips/mips.md (working copy)
@@ -415,7 +415,7 @@
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
@@ -748,6 +748,7 @@
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
+(include "xlr.md")
(include "generic.md")
;;
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c (revision 136391)
+++ gcc/config/mips/mips.c (working copy)
@@ -645,6 +645,7 @@
{ "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
{ "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
{ "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
+ { "xlr", PROCESSOR_XLR, 64, 0},
};
/* Default costs. If these are used for a processor we should look
@@ -1015,6 +1016,21 @@
{ /* SR71000 */
DEFAULT_COSTS
},
+ { /* XLR */
+ /* Need to replace first five with the costs of calling the appropriate
+ libgcc routine.*/
+ COSTS_N_INSNS (256), /* fp_add */
+ COSTS_N_INSNS (256), /* fp_mult_sf */
+ COSTS_N_INSNS (256), /* fp_mult_df */
+ COSTS_N_INSNS (256), /* fp_div_sf */
+ COSTS_N_INSNS (256), /* fp_div_df */
+ COSTS_N_INSNS (8), /* int_mult_si */
+ COSTS_N_INSNS (8), /* int_mult_di */
+ COSTS_N_INSNS (72), /* int_div_si */
+ COSTS_N_INSNS (72), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
};
/* This hash table keeps track of implicit "mips16" and "nomips16" attributes
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h (revision 136391)
+++ gcc/config/mips/mips.h (working copy)
@@ -69,6 +69,7 @@
PROCESSOR_SB1,
PROCESSOR_SB1A,
PROCESSOR_SR71000,
+ PROCESSOR_XLR,
PROCESSOR_MAX
};
2008-06-05 Sandip Matte <sandip@rmicorp.com>
* gcc/config/mips/xlr.md: New file for defining xlr processor automaton.
* gcc/config/mips/mips.md: New architecture xlr is added.
* gcc/config/mips/mips.h: Add definition for xlr processor.
* gcc/config/mips/mips.c: Add xlr processor entry in
mips_cpu_info_table and mips_rtx_cost_data.
* gcc/doc/invoke.texi: Add -march=xlr entry