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Changing the treatment of the MIPS HI and LO registers
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 27 May 2008 19:21:25 +0100
- Subject: Changing the treatment of the MIPS HI and LO registers
One of the main issues in porting IRA to MIPS is: how do we handle
HI and LO? We have traditionally treated them as separate registers,
but in many respects they aren't. Division instructions store
the quotient in LO and modulus in HI, but the LO result becomes
unpredictable after a following MTHI. The same is true for the
HI result after a following MTLO. The same is also true after
multiplication instructions that store a doubleword result
in HI and LO. The only way in which the registers are truly
independent is that the result of MTHI is unaffected by MFLO
and MTLO, and that the result of MTLO is unaffected by MFHI
and MFHI.
We have effectively been "hoping" that the high cost of MTHI, MTLO,
MFHI and MFLO would prevent moves into the HI and LO registers while
the other register is still live. This is very brittle and has
bugged me for ages. Unfortunately, I couldn't see an obvious
alternative that would:
(a) produce good code
(b) not introduce a difficult-to-maintain target hook, and
(c) preserve backwards compatibility.
We also rely on the costs for MIPS16, which doesn't have MTHI
and MTLO instructions at all.
I was recently shown a case in which a modified compiler did
allocate something to LO for MIPS16 and in which a move from
LO to a GPR was needed. (The modifications to the compiler
weren't responsible.) This proved the obvious: that relying
on costs for correctness wasn't safe.
Then there's IRA. We want HI, LO and GPRs to be in the same
cover class so that multiply-accumulate patterns work without
spilling to memory. As a consequence, IRA can sometimes use
HI and LO in cases where the current allocators wouldn't,
and I don't think IRA's wrong here.
Furthermore, moves to and from LO _are_ cheaper than (or as
cheap as) memory on some targets, so using it as spill space
on those targets is not necessarily a bad thing. This behaviour
would be conditional on -mtune.
The port to IRA has finally made me do something about this.
Unfortunately, though, I still can't see a way that does all three
of (a), (b) and (c) above. I've thought about various possible target
hooks, but:
- They all had dubious semantics.
- Any non-MIPS person working on the target-independent code would
soon forget about them.
- Even if we forgot to use the hook, the failure would probably only
show up rarely.
I thought about using special secondary-reload instructions to
move single-word values into HI or LO individually. These reload
instructions would clobber the "other" register, so the HI version
would look like:
(set (match_operand:... 0 "hi_operand" "=h")
(match_operand:... 1 "reg_or_0_operand" "dJ"))
(clobber (match_operand:... 2 "lo_operand" =l"))
and the LO version would be similar. Unfortunately, this triggers
chains of reloads that not currently supported; see push_secondary_reload.
It would also need some complicated code in the register allocators.
Even then, it wouldn't preserve total backwards compatibility,
because things like:
asm ("...." :: "h" (...single word...), "l" (...single word...)
asm ("...." : "=a" (...double word...) : "0" (...single word...))
would be impossible. (OK, we could get the second to work with even
more changes to reload, but...)
So in the end, I think the best thing would be to bite the bullet
and stop treating HI and LO as separate. The easiest way of doing
this is to prevent HI from storing single-word values, just as the
"old" 32-bit ISAs can't store single-word values in odd FPRs.
>From an implementation perspective, I think this is the least invasive
and most robust approach. Unfortunately, it's also the one that hurts
backwards compatibility the most. The "h" constraint would no longer
be available.
We can keep "hi" as a recognised register name for backwards compatibility
in clobber lists. (A lesson learned from removing the old on-the-side
"hilo" register, which had even more headaches than this one. After
that change, quite a few linux clobber lists had to be conditional on
the compiler version -- sorry about that!)
This patch does that, and has survived testing on mips64el-linux-gnu.
I ran it through CSiBE at -Os for the following options and very
few objects changed. Total sizes before and after were:
-EB -mabi=32 3868888 3868900 : +12
-EB -mabi=n32 3735396 3735360 : -36
-EB -mabi=64 3957380 3957260 : -120
-EB -march=vr4130 3792360 3792312 : -48
-EL -mabi=32 3868376 3868356 : -20
-EL -mabi=n32 3734436 3734352 : -84
-EL -mabi=64 3957012 3956924 : -88
-EL -march=vr4130 3791432 3791384 : -48
(The -march-less runs used -march=mips64.)
To be clear, the patch only solves the IRA issue; it doesn't solve
the MIPS16 one.
Two tests used "h" constraints to test for problems with the
separate treatment of HI and LO. There is no way of expressing
the same tests after the patch, so I've just removed them.
In a way, the tests now pass by design.
Comments? I'll hold off applying this for 48 hours to see if there
are any. If the patch goes in, I'll add something to the 4.4
changes page as well.
Richard
gcc/
* doc/md.texi: Synchronize with later constraints.md change.
* longlong.h (umul_ppmm): Replace the MIPS asm implementation
with a C implementation.
* config/mips/mips.c (mips_legitimize_move): Remove MFHI and
MFLO handling.
(mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT.
(mips_split_doubleword_move): Use special MTHI and MFHI instructions
when moving to and from MD_REGNUM.
(mips_output_move): Don't handle moves from GPRs to HI_REGNUM.
Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC.
Handle byte and halfword moves.
(mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS
separately.
* config/mips/constraints.md (h): Turn into NO_REGS.
* config/mips/mips.md (UNSPEC_MFHILO): Delete.
(UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New.
(UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber.
(HILO): New mode iterator.
(any_div): New code iterator.
(u): Extend code attribute to div and udiv.
(*add<mode>3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use
d_operand in the splitters. Remove redundant CONST_INT checks.
(mulsi3_mult3, mul<mode>3_internal, mul<mode>3_r4000, *mul_acc_si)
(*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si)
(*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits
accordingly, using normal moves instead of unspecs to move LO into
a GPR. Use d_operand and lo_operand instead of *_REG_P checks.
(<u>mulsidi3): Handle expansion in C code.
(<u>mulsidi3_32bit_internal): Rename to...
(<u>mulsidi3_32bit): ...this.
(*<u>mulsidi3_64bit): Rename to...
(<u>mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers
into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO
to set LO and HI to the multiplication result. Use a normal move
for MFLO and an unspec for MFHI.
(*<u>mulsidi3_64bit_parts): Replace with...
(<u>mulsidi3_64bit_hilo): ...this new instruction.
(<su>mulsi3_highpart): Turn into a define_insn_and_split and
force a GPR destination. Use MULHI if available, otherwise split
into a multiplication followed by an MFHI.
(<su>mulsi3_highpart_internal): Delete.
(<su>mulsi3_highpart_mulhi_internal): Likewise.
(*<su>mulsi3_highpart_neg_mulhi_internal): Remove the first alternative
and the "=h" clobber.
(<su>muldi3_highpart): Turn into a define_insn_and_split.
Force the destination to be a GPR and split it into two
instructions after reload.
(<u>mulditi3): New pattern.
(madsi): Remove "=h" clobber.
(divmod<mode>4, udivmod<mode>4): Turn into define_insn_and_splits.
Force the modulus result to be a GPR and split the instruction into
a division followed by an MFHI after reload.
(<u>divmod<GPR:mode>4_hilo_<HILO:mode>): New instruction.
(*lea_high64): Use d_operand in the define_peephole2. Likewise
the MIPS16 HIGH define_split.
(*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type
of acc<->gpr moves to "multi".
(*movdi_64bit): Replace the single "x" alternative with
alternatives for moving into and out of "a".
(*movhi_internal, *movqi_internal): Likewise. Use mips_output_move.
(*movsi_internal): Extend the "d<-A" alternative to "d<-a".
(*movhi_mips16, *movqi_mips16): Add d<-a alternatives.
Use mips_output_move. Use d_operand in the splitters.
Remove redundant CONST_INT checks.
(movti): New expander.
(*movti_internal): New define_insn_and_split.
(movtf, *movtf_internal): Require TARGET_64BIT.
(mfhilo_<mode>, *mfhilo_<mode>, *mfhilo_<mode>_macc): Delete.
(mfhi<GPR:mode>_<HILO:mode>): New pattern.
(mthi<GPR:mode>_<HILO:mode>): Likewise.
* config/mips/predicates.md (fpr_operand): Delete.
(d_operand): New predicate.
gcc/testsuite/
* gcc.dg/torture/mips-hilo-1.c: Delete.
* gcc.target/mips/pr35232.c: Likewise.
* gcc.target/mips/fix-vr4130-1.c: Use modulus to create an mfhi.
* gcc.target/mips/fix-vr4130-3.c: Likewise.
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi 2008-05-27 17:12:27.000000000 +0100
+++ gcc/doc/md.texi 2008-05-27 19:20:28.000000000 +0100
@@ -2495,7 +2495,7 @@ generating MIPS16 code.
A floating-point register (if available).
@item h
-The @code{hi} register.
+Formerly the @code{hi} register. This constraint is no longer supported.
@item l
The @code{lo} register.
Index: gcc/longlong.h
===================================================================
--- gcc/longlong.h 2008-05-27 17:12:27.000000000 +0100
+++ gcc/longlong.h 2008-05-27 19:20:28.000000000 +0100
@@ -623,12 +623,12 @@ #define UDIV_TIME 150
#endif /* __m88000__ */
#if defined (__mips__) && W_TYPE_SIZE == 32
-#define umul_ppmm(w1, w0, u, v) \
- __asm__ ("multu %2,%3" \
- : "=l" ((USItype) (w0)), \
- "=h" ((USItype) (w1)) \
- : "d" ((USItype) (u)), \
- "d" ((USItype) (v)))
+#define umul_ppmm(w1, w0, u, v) \
+ do { \
+ UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
+ (w1) = (USItype) (__x >> 32); \
+ (w0) = (USItype) (__x); \
+ } while (0)
#define UMUL_TIME 10
#define UDIV_TIME 100
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c 2008-05-27 17:12:27.000000000 +0100
+++ gcc/config/mips/mips.c 2008-05-27 19:20:48.000000000 +0100
@@ -2592,23 +2592,6 @@ mips_legitimize_move (enum machine_mode
return true;
}
- /* Check for individual, fully-reloaded mflo and mfhi instructions. */
- if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
- && REG_P (src) && MD_REG_P (REGNO (src))
- && REG_P (dest) && GP_REG_P (REGNO (dest)))
- {
- int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
- if (GET_MODE_SIZE (mode) <= 4)
- emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest),
- gen_lowpart (SImode, src),
- gen_rtx_REG (SImode, other_regno)));
- else
- emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest),
- gen_lowpart (DImode, src),
- gen_rtx_REG (DImode, other_regno)));
- return true;
- }
-
/* We need to deal with constants that would be legitimate
immediate_operands but aren't legitimate move_operands. */
if (CONSTANT_P (src) && !move_operand (src, mode))
@@ -3405,7 +3388,7 @@ mips_subword (rtx op, bool high_p)
mode = GET_MODE (op);
if (mode == VOIDmode)
- mode = DImode;
+ mode = TARGET_64BIT ? TImode : DImode;
if (TARGET_BIG_ENDIAN ? !high_p : high_p)
byte = UNITS_PER_WORD;
@@ -3456,6 +3439,8 @@ mips_split_64bit_move_p (rtx dest, rtx s
void
mips_split_doubleword_move (rtx dest, rtx src)
{
+ rtx low_dest;
+
if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
{
if (!TARGET_64BIT && GET_MODE (dest) == DImode)
@@ -3469,12 +3454,27 @@ mips_split_doubleword_move (rtx dest, rt
else
gcc_unreachable ();
}
+ else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
+ {
+ low_dest = mips_subword (dest, false);
+ mips_emit_move (low_dest, mips_subword (src, false));
+ if (TARGET_64BIT)
+ emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
+ else
+ emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
+ }
+ else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
+ {
+ mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
+ if (TARGET_64BIT)
+ emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
+ else
+ emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
+ }
else
{
/* The operation can be split into two normal moves. Decide in
which order to do them. */
- rtx low_dest;
-
low_dest = mips_subword (dest, false);
if (REG_P (low_dest)
&& reg_overlap_mentioned_p (low_dest, src))
@@ -3517,8 +3517,9 @@ mips_output_move (rtx dest, rtx src)
if (GP_REG_P (REGNO (dest)))
return "move\t%0,%z1";
- if (MD_REG_P (REGNO (dest)))
- return "mt%0\t%z1";
+ /* Moves to HI are handled by special .md insns. */
+ if (REGNO (dest) == LO_REGNUM)
+ return "mtlo\t%z1";
if (DSP_ACC_REG_P (REGNO (dest)))
{
@@ -3541,14 +3542,29 @@ mips_output_move (rtx dest, rtx src)
}
}
if (dest_code == MEM)
- return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0";
+ switch (GET_MODE_SIZE (mode))
+ {
+ case 1: return "sb\t%z1,%0";
+ case 2: return "sh\t%z1,%0";
+ case 4: return "sw\t%z1,%0";
+ case 8: return "sd\t%z1,%0";
+ }
}
if (dest_code == REG && GP_REG_P (REGNO (dest)))
{
if (src_code == REG)
{
- /* Handled by separate patterns. */
- gcc_assert (!MD_REG_P (REGNO (src)));
+ /* Moves from HI are handled by special .md insns. */
+ if (REGNO (src) == LO_REGNUM)
+ {
+ /* When generating VR4120 or VR4130 code, we use MACC and
+ DMACC instead of MFLO. This avoids both the normal
+ MIPS III HI/LO hazards and the errata related to
+ -mfix-vr4130. */
+ if (ISA_HAS_MACCHI)
+ return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
+ return "mflo\t%0";
+ }
if (DSP_ACC_REG_P (REGNO (src)))
{
@@ -3575,7 +3591,13 @@ mips_output_move (rtx dest, rtx src)
}
if (src_code == MEM)
- return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1";
+ switch (GET_MODE_SIZE (mode))
+ {
+ case 1: return "lbu\t%0,%1";
+ case 2: return "lhu\t%0,%1";
+ case 4: return "lw\t%0,%1";
+ case 8: return "ld\t%0,%1";
+ }
if (src_code == CONST_INT)
{
@@ -8851,13 +8873,30 @@ mips_hard_regno_mode_ok_p (unsigned int
if (ACC_REG_P (regno)
&& (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
{
- if (size <= UNITS_PER_WORD)
- return true;
+ if (MD_REG_P (regno))
+ {
+ /* After a multiplication or division, clobbering HI makes
+ the value of LO unpredictable, and vice versa. This means
+ that, for all interesting cases, HI and LO are effectively
+ a single register.
- if (size <= UNITS_PER_WORD * 2)
- return (DSP_ACC_REG_P (regno)
- ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
- : regno == MD_REG_FIRST);
+ We model this by requiring that any value that uses HI
+ also uses LO. */
+ if (size <= UNITS_PER_WORD * 2)
+ return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
+ }
+ else
+ {
+ /* DSP accumulators do not have the same restrictions as
+ HI and LO, so we can treat them as normal doubleword
+ registers. */
+ if (size <= UNITS_PER_WORD)
+ return true;
+
+ if (size <= UNITS_PER_WORD * 2
+ && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
+ return true;
+ }
}
if (ALL_COP_REG_P (regno))
Index: gcc/config/mips/constraints.md
===================================================================
--- gcc/config/mips/constraints.md 2008-05-27 17:12:27.000000000 +0100
+++ gcc/config/mips/constraints.md 2008-05-27 19:20:28.000000000 +0100
@@ -29,8 +29,8 @@ (define_register_constraint "t" "T_REG"
(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
"A floating-point register (if available).")
-(define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG"
- "The @code{hi} register.")
+(define_register_constraint "h" "NO_REGS"
+ "Formerly the @code{hi} register. This constraint is no longer supported.")
(define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
"The @code{lo} register.")
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md 2008-05-27 19:20:28.000000000 +0100
+++ gcc/config/mips/mips.md 2008-05-27 19:20:28.000000000 +0100
@@ -44,9 +44,11 @@ (define_constants
(UNSPEC_LOAD_CALL 23)
(UNSPEC_LOAD_GOT 24)
(UNSPEC_GP 25)
- (UNSPEC_MFHILO 26)
- (UNSPEC_TLS_LDM 27)
- (UNSPEC_TLS_GET_TP 28)
+ (UNSPEC_MFHI 26)
+ (UNSPEC_MTHI 27)
+ (UNSPEC_SET_HILO 28)
+ (UNSPEC_TLS_LDM 29)
+ (UNSPEC_TLS_GET_TP 30)
(UNSPEC_MFHC1 31)
(UNSPEC_MTHC1 32)
(UNSPEC_CLEAR_HAZARD 33)
@@ -484,6 +486,10 @@ (define_mode_iterator GPR [SI (DI "TARGE
;; modes.
(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+;; This mode iterator allows :HILO to be used as the mode of the
+;; concatenated HI and LO registers.
+(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
+
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
@@ -610,6 +616,10 @@ (define_code_iterator any_extend [sign_e
;; from the same template.
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
+;; This code iterator allows unsigned and signed division to be generated
+;; from the same template.
+(define_code_iterator any_div [div udiv])
+
;; This code iterator allows all native floating-point comparisons to be
;; generated from the same template.
(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
@@ -628,6 +638,7 @@ (define_code_iterator any_le [le leu])
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (div "") (udiv "u")
(gt "") (gtu "u")
(ge "") (geu "u")
(lt "") (ltu "u")
@@ -861,13 +872,10 @@ (define_insn "*add<mode>3_mips16"
;; simply adding a constant to a register.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
&& INTVAL (operands[1]) <= 0x7f + 0x7f)
|| (INTVAL (operands[1]) < - 0x80
@@ -890,16 +898,11 @@ (define_split
})
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (match_operand:SI 1 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && REG_P (operands[1])
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0x7f)
|| (INTVAL (operands[2]) < - 0x8
@@ -922,13 +925,10 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
&& INTVAL (operands[1]) <= 0xf + 0xf)
|| (INTVAL (operands[1]) < - 0x10
@@ -951,16 +951,11 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
+ (plus:DI (match_operand:DI 1 "d_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && REG_P (operands[1])
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0xf)
|| (INTVAL (operands[2]) < - 0x8
@@ -1171,8 +1166,7 @@ (define_insn "mulsi3_mult3"
[(set (match_operand:SI 0 "register_operand" "=d,l")
(mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d")))
- (clobber (match_scratch:SI 3 "=h,h"))
- (clobber (match_scratch:SI 4 "=l,X"))]
+ (clobber (match_scratch:SI 3 "=l,X"))]
"ISA_HAS_MUL3"
{
if (which_alternative == 1)
@@ -1191,30 +1185,26 @@ (define_insn "mulsi3_mult3"
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
-;; Operand 3: HI
-;; Operand 4: GPR (destination)
+;; Operand 3: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
(clobber (scratch:SI))])
- (set (match_operand:SI 4 "register_operand")
- (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
[(parallel
- [(set (match_dup 4)
+ [(set (match_dup 3)
(mult:SI (match_dup 1)
(match_dup 2)))
- (clobber (match_dup 3))
(clobber (match_dup 0))])])
(define_insn "mul<mode>3_internal"
[(set (match_operand:GPR 0 "register_operand" "=l")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "register_operand" "d")))
- (clobber (match_scratch:GPR 3 "=h"))]
+ (match_operand:GPR 2 "register_operand" "d")))]
"!TARGET_FIX_R4000"
"<d>mult\t%1,%2"
[(set_attr "type" "imul")
@@ -1224,8 +1214,7 @@ (define_insn "mul<mode>3_r4000"
[(set (match_operand:GPR 0 "register_operand" "=d")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (clobber (match_scratch:GPR 3 "=h"))
- (clobber (match_scratch:GPR 4 "=l"))]
+ (clobber (match_scratch:GPR 3 "=l"))]
"TARGET_FIX_R4000"
"<d>mult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul")
@@ -1239,16 +1228,13 @@ (define_insn "mul<mode>3_r4000"
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
-;; Operand 3: HI
-;; Operand 4: GPR (destination)
+;; Operand 3: GPR (destination)
(define_peephole2
- [(parallel
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))])
- (set (match_operand:SI 4 "register_operand")
- (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
"ISA_HAS_MACC && !ISA_HAS_MUL3"
[(set (match_dup 0)
(const_int 0))
@@ -1257,11 +1243,10 @@ (define_peephole2
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
(match_dup 0)))
- (set (match_dup 4)
+ (set (match_dup 3)
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
- (match_dup 0)))
- (clobber (match_dup 3))])])
+ (match_dup 0)))])])
;; Multiply-accumulate patterns
@@ -1280,9 +1265,8 @@ (define_insn "*mul_acc_si"
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
(match_operand:SI 2 "register_operand" "d,d,d"))
(match_operand:SI 3 "register_operand" "0,l,*d")))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,3,l"))
- (clobber (match_scratch:SI 6 "=X,X,&d"))]
+ (clobber (match_scratch:SI 4 "=X,3,l"))
+ (clobber (match_scratch:SI 5 "=X,X,&d"))]
"(TARGET_MIPS3900
|| GENERATE_MADD_MSUB)
&& !TARGET_MIPS16"
@@ -1298,53 +1282,45 @@ (define_insn "*mul_acc_si"
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
-;; Split the above insn if we failed to get LO allocated.
+;; Split *mul_acc_si if both the source and destination accumulator
+;; values are GPRs.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
- (match_operand:SI 3 "register_operand")))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[3]))"
- [(parallel [(set (match_dup 6)
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_operand:SI 3 "d_operand")))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed && !TARGET_DEBUG_D_MODE"
+ [(parallel [(set (match_dup 5)
(mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])
- (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
"")
-;; Splitter to copy result of MADD to a general register
+;; Split *mul_acc_si if the destination accumulator value is in a GPR
+;; and the source accumulator value is in LO.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
- (match_operand:SI 3 "register_operand")))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[3]) == LO_REGNUM"
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_operand:SI 3 "lo_operand")))
+ (clobber (match_dup 3))
+ (clobber (scratch:SI))]
+ "reload_completed && !TARGET_DEBUG_D_MODE"
[(parallel [(set (match_dup 3)
(plus:SI (mult:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
- "")
+ (clobber (scratch:SI))
+ (clobber (scratch:SI))])
+ (set (match_dup 0) (match_dup 3))])
(define_insn "*macc"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))
(match_operand:SI 3 "register_operand" "0,l")))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,3"))]
+ (clobber (match_scratch:SI 4 "=X,3"))]
"ISA_HAS_MACC"
{
if (which_alternative == 1)
@@ -1365,8 +1341,7 @@ (define_insn "*msac"
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,1"))]
+ (clobber (match_scratch:SI 4 "=X,1"))]
"ISA_HAS_MSAC"
{
if (which_alternative == 1)
@@ -1385,21 +1360,19 @@ (define_insn_and_split "*msac_using_macc
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,1"))
- (clobber (match_scratch:SI 6 "=d,d"))]
+ (clobber (match_scratch:SI 4 "=X,1"))
+ (clobber (match_scratch:SI 5 "=d,d"))]
"ISA_HAS_MACC && !ISA_HAS_MSAC"
"#"
"&& reload_completed"
- [(set (match_dup 6)
+ [(set (match_dup 5)
(neg:SI (match_dup 3)))
(parallel
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 2)
- (match_dup 6))
+ (match_dup 5))
(match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])]
+ (clobber (match_dup 4))])]
""
[(set_attr "type" "imadd")
(set_attr "length" "8")])
@@ -1414,8 +1387,7 @@ (define_insn "*macc2"
(set (match_operand:SI 3 "register_operand" "=d")
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
- (match_dup 0)))
- (clobber (match_scratch:SI 4 "=h"))]
+ (match_dup 0)))]
"ISA_HAS_MACC && reload_completed"
"macc\t%3,%1,%2"
[(set_attr "type" "imadd")
@@ -1429,8 +1401,7 @@ (define_insn "*msac2"
(set (match_operand:SI 3 "register_operand" "=d")
(minus:SI (match_dup 0)
(mult:SI (match_dup 1)
- (match_dup 2))))
- (clobber (match_scratch:SI 4 "=h"))]
+ (match_dup 2))))]
"ISA_HAS_MSAC && reload_completed"
"msac\t%3,%1,%2"
[(set_attr "type" "imadd")
@@ -1441,23 +1412,19 @@ (define_insn "*msac2"
;;
;; Operand 0: LO
;; Operand 1: macc/msac
-;; Operand 2: HI
-;; Operand 3: GPR (destination)
+;; Operand 2: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "lo_operand")
(match_operand:SI 1 "macc_msac_operand"))
- (clobber (match_operand:SI 2 "register_operand"))
(clobber (scratch:SI))])
- (set (match_operand:SI 3 "register_operand")
- (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 2 "d_operand")
+ (match_dup 0))]
""
[(parallel [(set (match_dup 0)
(match_dup 1))
- (set (match_dup 3)
- (match_dup 1))
- (clobber (match_dup 2))])]
- "")
+ (set (match_dup 2)
+ (match_dup 1))])])
;; When we have a three-address multiplication instruction, it should
;; be faster to do a separate multiply and add, rather than moving
@@ -1471,32 +1438,26 @@ (define_peephole2
;; Operand 2: GPR (addend)
;; Operand 3: GPR (destination)
;; Operand 4: macc/msac
-;; Operand 5: HI
-;; Operand 6: new multiplication
-;; Operand 7: new addition/subtraction
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
- [(set (match_operand:SI 3 "register_operand")
+ [(set (match_operand:SI 3 "d_operand")
(match_operand:SI 4 "macc_msac_operand"))
- (clobber (match_operand:SI 5 "register_operand"))
(clobber (match_dup 1))])]
- "ISA_HAS_MUL3
- && true_regnum (operands[1]) == LO_REGNUM
- && peep2_reg_dead_p (2, operands[1])
- && GP_REG_P (true_regnum (operands[3]))"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
[(parallel [(set (match_dup 0)
- (match_dup 6))
- (clobber (match_dup 5))
+ (match_dup 5))
(clobber (match_dup 1))])
(set (match_dup 3)
- (match_dup 7))]
+ (match_dup 6))]
{
- operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
- operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
+ operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
operands[2], operands[0]);
})
@@ -1506,33 +1467,30 @@ (define_peephole2
;; Operand 1: LO
;; Operand 2: GPR (addend)
;; Operand 3: macc/msac
-;; Operand 4: HI
-;; Operand 5: GPR (destination)
-;; Operand 6: new multiplication
-;; Operand 7: new addition/subtraction
+;; Operand 4: GPR (destination)
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
[(set (match_dup 1)
(match_operand:SI 3 "macc_msac_operand"))
- (clobber (match_operand:SI 4 "register_operand"))
(clobber (scratch:SI))])
(match_dup 0)
- (set (match_operand:SI 5 "register_operand")
- (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 4 "d_operand")
+ (match_dup 1))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
- (match_dup 6))
- (clobber (match_dup 4))
+ (match_dup 5))
(clobber (match_dup 1))])
- (set (match_dup 5)
- (match_dup 7))]
+ (set (match_dup 4)
+ (match_dup 6))]
{
- operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
- operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
+ operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
operands[2], operands[0]);
})
@@ -1541,9 +1499,8 @@ (define_insn "*mul_sub_si"
(minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
(mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
(match_operand:SI 3 "register_operand" "d,d,d"))))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,1,l"))
- (clobber (match_scratch:SI 6 "=X,X,&d"))]
+ (clobber (match_scratch:SI 4 "=X,1,l"))
+ (clobber (match_scratch:SI 5 "=X,X,&d"))]
"GENERATE_MADD_MSUB"
"@
msub\t%2,%3
@@ -1553,52 +1510,45 @@ (define_insn "*mul_sub_si"
(set_attr "mode" "SI")
(set_attr "length" "4,8,8")])
-;; Split the above insn if we failed to get LO allocated.
+;; Split *mul_sub_si if both the source and destination accumulator
+;; values are GPRs.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (mult:SI (match_operand:SI 2 "register_operand")
- (match_operand:SI 3 "register_operand"))))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[1]))"
- [(parallel [(set (match_dup 6)
+ [(set (match_operand:SI 0 "d_operand")
+ (minus:SI (match_operand:SI 1 "d_operand")
+ (mult:SI (match_operand:SI 2 "d_operand")
+ (match_operand:SI 3 "d_operand"))))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed && !TARGET_DEBUG_D_MODE"
+ [(parallel [(set (match_dup 5)
(mult:SI (match_dup 2) (match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
"")
-;; Splitter to copy result of MSUB to a general register
+;; Split *mul_acc_si if the destination accumulator value is in a GPR
+;; and the source accumulator value is in LO.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (mult:SI (match_operand:SI 2 "register_operand")
- (match_operand:SI 3 "register_operand"))))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[1]) == LO_REGNUM"
+ [(set (match_operand:SI 0 "d_operand")
+ (minus:SI (match_operand:SI 1 "lo_operand")
+ (mult:SI (match_operand:SI 2 "d_operand")
+ (match_operand:SI 3 "d_operand"))))
+ (clobber (match_dup 1))
+ (clobber (scratch:SI))]
+ "reload_completed && !TARGET_DEBUG_D_MODE"
[(parallel [(set (match_dup 1)
(minus:SI (match_dup 1)
(mult:SI (match_dup 2) (match_dup 3))))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
+ (clobber (scratch:SI))
+ (clobber (scratch:SI))])
+ (set (match_dup 0) (match_dup 1))]
"")
(define_insn "*muls"
- [(set (match_operand:SI 0 "register_operand" "=l,d")
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
(neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 3 "=h,h"))
- (clobber (match_scratch:SI 4 "=X,l"))]
+ (clobber (match_scratch:SI 3 "=X,l"))]
"ISA_HAS_MULS"
"@
muls\t$0,%1,%2
@@ -1606,31 +1556,23 @@ (define_insn "*muls"
[(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
-;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
-
(define_expand "<u>mulsidi3"
- [(parallel
- [(set (match_operand:DI 0 "register_operand")
- (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
- (any_extend:DI (match_operand:SI 2 "register_operand"))))
- (clobber (scratch:DI))
- (clobber (scratch:DI))
- (clobber (scratch:DI))])]
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
+ (any_extend:DI (match_operand:SI 2 "register_operand"))))]
"!TARGET_64BIT || !TARGET_FIX_R4000"
{
- if (!TARGET_64BIT)
- {
- if (!TARGET_FIX_R4000)
- emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
- operands[2]));
- else
- emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
+ if (TARGET_64BIT)
+ emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
+ DONE;
})
-(define_insn "<u>mulsidi3_32bit_internal"
+(define_insn "<u>mulsidi3_32bit"
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
@@ -1650,37 +1592,30 @@ (define_insn "<u>mulsidi3_32bit_r4000"
(set_attr "mode" "SI")
(set_attr "length" "12")])
-(define_insn_and_split "*<u>mulsidi3_64bit"
+(define_insn_and_split "<u>mulsidi3_64bit"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=h"))
- (clobber (match_scratch:DI 5 "=d"))]
+ (clobber (match_scratch:TI 3 "=x"))
+ (clobber (match_scratch:DI 4 "=d"))]
"TARGET_64BIT && !TARGET_FIX_R4000"
"#"
"&& reload_completed"
- [(parallel
- [(set (match_dup 3)
- (sign_extend:DI
- (mult:SI (match_dup 1)
- (match_dup 2))))
- (set (match_dup 4)
- (ashiftrt:DI
- (mult:DI (any_extend:DI (match_dup 1))
- (any_extend:DI (match_dup 2)))
- (const_int 32)))])
-
- ;; OP5 <- LO, OP0 <- HI
- (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
- (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
-
- ;; Zero-extend OP5.
- (set (match_dup 5)
- (ashift:DI (match_dup 5)
+ [(set (match_dup 3)
+ (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
+ (any_extend:DI (match_dup 2)))]
+ UNSPEC_SET_HILO))
+
+ ;; OP4 <- LO, OP0 <- HI
+ (set (match_dup 4) (match_dup 5))
+ (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
+
+ ;; Zero-extend OP4.
+ (set (match_dup 4)
+ (ashift:DI (match_dup 4)
(const_int 32)))
- (set (match_dup 5)
- (lshiftrt:DI (match_dup 5)
+ (set (match_dup 4)
+ (lshiftrt:DI (match_dup 4)
(const_int 32)))
;; Shift OP0 into place.
@@ -1691,24 +1626,21 @@ (define_insn_and_split "*<u>mulsidi3_64b
;; OR the two halves together
(set (match_dup 0)
(ior:DI (match_dup 0)
- (match_dup 5)))]
- ""
+ (match_dup 4)))]
+ { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "24")])
-(define_insn "*<u>mulsidi3_64bit_parts"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (sign_extend:DI
- (mult:SI (match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d"))))
- (set (match_operand:DI 1 "register_operand" "=h")
- (ashiftrt:DI
- (mult:DI (any_extend:DI (match_dup 2))
- (any_extend:DI (match_dup 3)))
- (const_int 32)))]
+(define_insn "<u>mulsidi3_64bit_hilo"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (unspec:TI
+ [(mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
+ UNSPEC_SET_HILO))]
"TARGET_64BIT && !TARGET_FIX_R4000"
- "mult<u>\t%2,%3"
+ "mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -1745,87 +1677,83 @@ (define_insn "<u>msubsidi4"
;; _highpart patterns
-(define_expand "<su>mulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
- (any_extend:DI (match_operand:SI 2 "register_operand")))
- (const_int 32))))]
- "ISA_HAS_MULHI || !TARGET_FIX_R4000"
-{
- if (ISA_HAS_MULHI)
- emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
- operands[1],
- operands[2]));
- else
- emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
- operands[2]));
- DONE;
-})
-
-(define_insn "<su>mulsi3_highpart_internal"
- [(set (match_operand:SI 0 "register_operand" "=h")
- (truncate:SI
+(define_insn_and_split "<su>mulsi3_highpart"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (truncate:SI
(lshiftrt:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=l"))]
- "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
- "mult<u>\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+ "ISA_HAS_MULHI || !TARGET_FIX_R4000"
+ { return ISA_HAS_MULHI ? "mulhi<u>\t%0,%1,%2" : "#"; }
+ "&& reload_completed && !ISA_HAS_MULHI"
+ [(const_int 0)]
+{
+ rtx hilo;
-(define_insn "<su>mulsi3_highpart_mulhi_internal"
- [(set (match_operand:SI 0 "register_operand" "=h,d")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
- (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=l,l"))
- (clobber (match_scratch:SI 4 "=X,h"))]
- "ISA_HAS_MULHI"
- "@
- mult<u>\t%1,%2
- mulhi<u>\t%0,%1,%2"
- [(set_attr "type" "imul,imul3")
- (set_attr "mode" "SI")])
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_ti (operands[0], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_di (operands[0], hilo));
+ }
+ DONE;
+})
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
- [(set (match_operand:SI 0 "register_operand" "=h,d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(neg:DI
(mult:DI
- (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
- (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=l,l"))
- (clobber (match_scratch:SI 4 "=X,h"))]
+ (clobber (match_scratch:SI 3 "=l"))]
"ISA_HAS_MULHI"
- "@
- mulshi<u>\t%.,%1,%2
- mulshi<u>\t%0,%1,%2"
- [(set_attr "type" "imul,imul3")
+ "mulshi<u>\t%0,%1,%2"
+ [(set_attr "type" "imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
;; errata MD(0), which says that dmultu does not always produce the
;; correct result.
-(define_insn "<su>muldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=h")
+(define_insn_and_split "<su>muldi3_highpart"
+ [(set (match_operand:DI 0 "register_operand" "=d")
(truncate:DI
(lshiftrt:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
- (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=l"))]
"TARGET_64BIT && !TARGET_FIX_R4000
&& !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulditi3 (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhidi_ti (operands[0], hilo));
+ DONE;
+})
+
+(define_insn "<u>mulditi3"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (mult:TI
+ (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
+ "TARGET_64BIT && !TARGET_FIX_R4000
+ && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -1837,8 +1765,7 @@ (define_insn "madsi"
[(set (match_operand:SI 0 "register_operand" "+l")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))
- (match_dup 0)))
- (clobber (match_scratch:SI 3 "=h"))]
+ (match_dup 0)))]
"TARGET_MAD"
"mad\t%1,%2"
[(set_attr "type" "imadd")
@@ -2013,29 +1940,74 @@ (define_insn "*recip<mode>3"
;; VR4120 errata MD(A1): signed division instructions do not work correctly
;; with negative operands. We use special libgcc functions instead.
-(define_insn "divmod<mode>4"
+(define_insn_and_split "divmod<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (set (match_operand:GPR 3 "register_operand" "=h")
+ (set (match_operand:GPR 3 "register_operand" "=d")
(mod:GPR (match_dup 1)
(match_dup 2)))]
"!TARGET_FIX_VR4120"
- { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
- [(set_attr "type" "idiv")
- (set_attr "mode" "<MODE>")])
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
+ }
+ DONE;
+})
-(define_insn "udivmod<mode>4"
+(define_insn_and_split "udivmod<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(udiv:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (set (match_operand:GPR 3 "register_operand" "=h")
+ (set (match_operand:GPR 3 "register_operand" "=d")
(umod:GPR (match_dup 1)
(match_dup 2)))]
""
- { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
+ }
+ DONE;
+})
+
+(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO
+ [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d"))]
+ UNSPEC_SET_HILO))]
+ ""
+ { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
[(set_attr "type" "idiv")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
;;
;; ....................
@@ -3237,7 +3209,7 @@ (define_insn_and_split "*lea_high64"
;; dsll32 op1,op1,0
;; daddu op1,op1,op0
(define_peephole2
- [(set (match_operand:DI 1 "register_operand")
+ [(set (match_operand:DI 1 "d_operand")
(high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
(match_scratch:DI 0 "d")]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
@@ -3290,8 +3262,8 @@ (define_insn_and_split "*lea64"
;;
;; on MIPS16 targets.
(define_split
- [(set (match_operand:SI 0 "register_operand" "=d")
- (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
+ [(set (match_operand:SI 0 "d_operand")
+ (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
"TARGET_MIPS16 && reload_completed"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
@@ -3460,7 +3432,7 @@ (define_insn "*movdi_32bit"
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
+ [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,load,mfc,store")
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
@@ -3471,7 +3443,7 @@ (define_insn "*movdi_gp32_fp64"
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+ [(set_attr "type" "multi,multi,load,store,multi,multi,mtc,fpload,mfc,fpstore")
(set_attr "mode" "DI")
(set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
@@ -3482,20 +3454,20 @@ (define_insn "*movdi_32bit_mips16"
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
+ [(set_attr "type" "multi,multi,multi,multi,multi,load,store,multi")
(set_attr "mode" "DI")
(set_attr "length" "8,8,8,8,12,*,*,8")])
(define_insn "*movdi_64bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
- (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
"TARGET_64BIT && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
+ [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,load,mfc,store")
(set_attr "mode" "DI")
- (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
+ (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,8,*,8,*")])
(define_insn "*movdi_64bit_mips16"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
@@ -3527,14 +3499,11 @@ (define_insn "*movdi_64bit_mips16"
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:DI 0 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
(mem:DI (plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x10)
|| (INTVAL (operands[1]) >= 32 * 8
@@ -3585,7 +3554,7 @@ (define_expand "movsi"
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
- (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
+ (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
@@ -3623,13 +3592,10 @@ (define_insn "*movsi_mips16"
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(mem:SI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32 * 4
@@ -3665,12 +3631,9 @@ (define_split
;; instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) >= 0x100
&& INTVAL (operands[1]) <= 0xff + 0x7f"
[(set (match_dup 0) (match_dup 1))
@@ -3793,36 +3756,24 @@ (define_expand "movhi"
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
- (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
- "@
- move\t%0,%1
- li\t%0,%1
- lhu\t%0,%1
- sh\t%z1,%0
- mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mthilo")
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "move,arith,load,store,mthilo,mfhilo")
(set_attr "mode" "HI")
- (set_attr "length" "4,4,*,*,4")])
+ (set_attr "length" "4,4,*,*,4,4")])
(define_insn "*movhi_mips16"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
- (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
"TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
- "@
- move\t%0,%1
- move\t%0,%1
- move\t%0,%1
- li\t%0,%1
- #
- lhu\t%0,%1
- sh\t%1,%0"
- [(set_attr "type" "move,move,move,arith,arith,load,store")
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo")
(set_attr "mode" "HI")
(set_attr_alternative "length"
[(const_int 4)
@@ -3835,6 +3786,7 @@ (define_insn "*movhi_mips16"
(const_int 8)
(const_int 12))
(const_string "*")
+ (const_string "*")
(const_string "*")])])
@@ -3843,13 +3795,10 @@ (define_insn "*movhi_mips16"
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:HI 0 "register_operand")
+ [(set (match_operand:HI 0 "d_operand")
(mem:HI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32 * 2
@@ -3897,51 +3846,36 @@ (define_expand "movqi"
})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
- (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
- "@
- move\t%0,%1
- li\t%0,%1
- lbu\t%0,%1
- sb\t%z1,%0
- mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mthilo")
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "move,arith,load,store,mthilo,mfhilo")
(set_attr "mode" "QI")
- (set_attr "length" "4,4,*,*,4")])
+ (set_attr "length" "4,4,*,*,4,4")])
(define_insn "*movqi_mips16"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
- (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
"TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
- "@
- move\t%0,%1
- move\t%0,%1
- move\t%0,%1
- li\t%0,%1
- #
- lbu\t%0,%1
- sb\t%1,%0"
- [(set_attr "type" "move,move,move,arith,arith,load,store")
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "type" "move,move,move,arith,arith,load,store,mfhilo")
(set_attr "mode" "QI")
- (set_attr "length" "4,4,4,4,8,*,*")])
+ (set_attr "length" "4,4,4,4,8,*,*,4")])
;; On the mips16, we can split lb $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:QI 0 "register_operand")
+ [(set (match_operand:QI 0 "d_operand")
(mem:QI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32
@@ -4061,12 +3995,37 @@ (define_insn "*movdf_mips16"
(set_attr "mode" "DF")
(set_attr "length" "8,8,8,*,*")])
+;; 128-bit integer moves
+
+(define_expand "movti"
+ [(set (match_operand:TI 0)
+ (match_operand:TI 1))]
+ "TARGET_64BIT"
+{
+ if (mips_legitimize_move (TImode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn_and_split "*movti_internal"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,R,*a,*d")
+ (match_operand:TI 1 "move_operand" "diR,dJ,*d*J,*a"))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ mips_split_doubleword_move (operands[0], operands[1]);
+ DONE;
+}
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")])
+
;; 128-bit floating point moves
(define_expand "movtf"
[(set (match_operand:TF 0 "")
(match_operand:TF 1 ""))]
- ""
+ "TARGET_64BIT"
{
if (mips_legitimize_move (TFmode, operands[0], operands[1]))
DONE;
@@ -4076,7 +4035,7 @@ (define_expand "movtf"
(define_insn_and_split "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=d,R,f,dR")
(match_operand:TF 1 "move_operand" "dGR,dG,dGR,f"))]
- ""
+ "TARGET_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -4101,7 +4060,7 @@ (define_split
;; When generating mips16 code, split moves of negative constants into
;; a positive "li" followed by a negation.
(define_split
- [(set (match_operand 0 "register_operand")
+ [(set (match_operand 0 "d_operand")
(match_operand 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
[(set (match_dup 2)
@@ -4150,44 +4109,27 @@ (define_insn "movv2sf_hardfloat_32bit"
(set_attr "mode" "SF")
(set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
-;; The HI and LO registers are not truly independent. If we move an mthi
-;; instruction before an mflo instruction, it will make the result of the
-;; mflo unpredictable. The same goes for mtlo and mfhi.
-;;
-;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
-;; Operand 1 is the register we want, operand 2 is the other one.
-;;
-;; When generating VR4120 or VR4130 code, we use macc{,hi} and
-;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
-;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
-
-(define_expand "mfhilo_<mode>"
- [(set (match_operand:GPR 0 "register_operand")
- (unspec:GPR [(match_operand:GPR 1 "register_operand")
- (match_operand:GPR 2 "register_operand")]
- UNSPEC_MFHILO))])
-
-(define_insn "*mfhilo_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
- (match_operand:GPR 2 "register_operand" "l,h")]
- UNSPEC_MFHILO))]
- "!ISA_HAS_MACCHI"
- "mf%1\t%0"
+;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
+;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
+;; and the errata related to -mfix-vr4130.
+(define_insn "mfhi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
+ UNSPEC_MFHI))]
+ ""
+ { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
[(set_attr "type" "mfhilo")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*mfhilo_<mode>_macc"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
- (match_operand:GPR 2 "register_operand" "l,h")]
- UNSPEC_MFHILO))]
- "ISA_HAS_MACCHI"
- "@
- <d>macchi\t%0,%.,%.
- <d>macc\t%0,%.,%."
- [(set_attr "type" "mfhilo")
- (set_attr "mode" "<MODE>")])
+(define_insn "mthi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:GPR 2 "register_operand" "l")]
+ UNSPEC_MTHI))]
+ ""
+ "mthi\t%z1"
+ [(set_attr "type" "mthilo")
+ (set_attr "mode" "SI")])
;; Emit a doubleword move in which exactly one of the operands is
;; a floating-point register. We can't just emit two normal moves
@@ -5099,11 +5041,10 @@ (define_insn "*lshrdi3_mips16"
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:GPR 0 "register_operand")
- (any_shift:GPR (match_operand:GPR 1 "register_operand")
+ [(set (match_operand:GPR 0 "d_operand")
+ (any_shift:GPR (match_operand:GPR 1 "d_operand")
(match_operand:GPR 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
Index: gcc/config/mips/predicates.md
===================================================================
--- gcc/config/mips/predicates.md 2008-05-27 17:12:27.000000000 +0100
+++ gcc/config/mips/predicates.md 2008-05-27 19:20:28.000000000 +0100
@@ -76,9 +76,11 @@ (define_predicate "const_0_or_1_operand"
(ior (match_test "op == CONST0_RTX (GET_MODE (op))")
(match_test "op == CONST1_RTX (GET_MODE (op))"))))
-(define_predicate "fpr_operand"
+(define_predicate "d_operand"
(and (match_code "reg")
- (match_test "FP_REG_P (REGNO (op))")))
+ (match_test "TARGET_MIPS16
+ ? M16_REG_P (REGNO (op))
+ : GP_REG_P (REGNO (op))")))
(define_predicate "lo_operand"
(and (match_code "reg")
Index: gcc/testsuite/gcc.dg/torture/mips-hilo-1.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/mips-hilo-1.c 2008-05-27 17:12:27.000000000 +0100
+++ /dev/null 2008-05-22 09:18:20.560097500 +0100
@@ -1,73 +0,0 @@
-/* f1 checks that an mtlo is not moved before an mfhi. f2 does the same
- for an mthi and an mflo. */
-/* { dg-do run { target mips*-*-* } } */
-/* { dg-options "-mtune=rm7000" } */
-
-extern void abort (void);
-extern void exit (int);
-
-#define DECLARE(TYPE) \
- TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \
- f1##TYPE (TYPE x1, TYPE x2, TYPE x3) \
- { \
- TYPE t1, t2; \
- \
- asm ("mult\t%1,%2" : "=h" (t1) : "d" (x1), "d" (x2) : "lo"); \
- asm ("mflo\t%0" : "=r" (t2) : "l" (x3) : "hi"); \
- return t1 + t2; \
- } \
- \
- TYPE __attribute__ ((noinline)) __attribute__ ((nomips16)) \
- f2##TYPE (TYPE x1, TYPE x2, TYPE x3) \
- { \
- TYPE t1, t2; \
- \
- asm ("mult\t%1,%2" : "=l" (t1) : "d" (x1), "d" (x2) : "hi"); \
- asm ("mfhi\t%0" : "=r" (t2) : "h" (x3) : "lo"); \
- return t1 + t2; \
- }
-
-#define TEST(TYPE) \
- if (f1##TYPE (1, 2, 10) != 10) \
- abort (); \
- if (f2##TYPE (1, 2, 40) != 42) \
- abort ()
-
-typedef char c;
-typedef signed char sc;
-typedef unsigned char uc;
-typedef short s;
-typedef unsigned short us;
-typedef int i;
-typedef unsigned int ui;
-typedef long long ll;
-typedef unsigned long long ull;
-
-DECLARE (c)
-DECLARE (sc)
-DECLARE (uc)
-DECLARE (s)
-DECLARE (us)
-DECLARE (i)
-DECLARE (ui)
-#if defined (__mips64)
-DECLARE (ll)
-DECLARE (ull)
-#endif
-
-int
-main ()
-{
- TEST (c);
- TEST (sc);
- TEST (uc);
- TEST (s);
- TEST (us);
- TEST (i);
- TEST (ui);
-#if defined (__mips64)
- TEST (ll);
- TEST (ull);
-#endif
- exit (0);
-}
Index: gcc/testsuite/gcc.target/mips/pr35232.c
===================================================================
--- gcc/testsuite/gcc.target/mips/pr35232.c 2008-05-27 17:12:27.000000000 +0100
+++ /dev/null 2008-05-22 09:18:20.560097500 +0100
@@ -1,17 +0,0 @@
-/* { dg-do run } */
-/* { dg-mips-options "-O" } */
-
-NOMIPS16 unsigned int
-f1 (unsigned long long x)
-{
- unsigned int r;
- asm ("# %0" : "=a" (r) : "0" (x));
- asm ("# %0" : "=h" (r) : "0" (r));
- return r;
-}
-
-int
-main (void)
-{
- return f1 (4) != 4;
-}
Index: gcc/testsuite/gcc.target/mips/fix-vr4130-1.c
===================================================================
--- gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-05-27 17:12:27.000000000 +0100
+++ gcc/testsuite/gcc.target/mips/fix-vr4130-1.c 2008-05-27 19:20:28.000000000 +0100
@@ -1,4 +1,8 @@
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */
-NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; }
+NOMIPS16 unsigned int
+foo (unsigned int x, unsigned int y)
+{
+ return x % y;
+}
/* { dg-final { scan-assembler "\tmacchi\t" } } */
Index: gcc/testsuite/gcc.target/mips/fix-vr4130-3.c
===================================================================
--- gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-05-27 17:12:27.000000000 +0100
+++ gcc/testsuite/gcc.target/mips/fix-vr4130-3.c 2008-05-27 19:20:28.000000000 +0100
@@ -1,10 +1,8 @@
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
-NOMIPS16 long long
-foo (void)
+NOMIPS16 unsigned long long
+foo (unsigned long long x, unsigned long long y)
{
- long long r;
- asm ("# foo" : "=h" (r));
- return r;
+ return x % y;
}
/* { dg-final { scan-assembler "\tdmacchi\t" } } */