Re: [PATCH; RFC] Alignment of component_ref's.

[Adam Nemet <anemet at caviumnetworks dot com>]

Maxim Kuvyrkov writes:
> Here's an example (g is garbage, D is field we want to store to):
> 
> 01234578
> gggDDDDg
> 
> 1. If using 1-byte alignment, we'll get 4 stores.
> 2. If using 2-byte alignment, we'll get 2 loads, 3 stores and a bunch of 
> bit operations.
> 3. If using 4-byte alignment, we'll get 2 loads, 2 stores and bit 
> operations.
> 4. If using 8-byte alignment, we'll get 1 load, 1 store and bit operations.
> 
> The best choice is either (1) or (4).  Though, (4) is a good choice only 
> if target supports 64-bit memory operations.

1. should ideally use swl and swr so it is only two stores.  Also 1. provides
more scheduling freedom than the read-modify-write cases.

> Unfortunately, there's no reliable way to say if the reference is read 
> or write.  One possible way is to use the fact that 
> set_mem_attributes_minus_bitpos is called with non-zero bitpos only for 
> write references, so the above example should never come up for a read 
> reference.  The minus is that can change in the future.

Instead of decreasing the alignment of the mem expression itself maybe you can
modify where the actual store is expanded (store_field?) and make a better
decision there.

Adam