Re: Update SSE5 vector multiplication, shift, rotate, take 2

[Michael Meissner <michael dot meissner at amd dot com>]

This is re-opening up the discussion started with this thread:
http://gcc.gnu.org/ml/gcc-patches/2008-04/msg01387.html

I recently got back to these changes.  To recap, Richard G. asked for no new
tree codes, and I recoded the patch to not need the new tree codes.  However,
it breaks the other two ports that have vector/vector shifts (SPU, PowerPC).
So it looks like the changes to eliminate the extra tree codes will involve
more work.  Basically, all of the places that call optab_for_tree_code will
need to be recoded or at least looked at:
     expr.c
     tree-vect-analyze.c
     tree-vect-generic.c
     tree-vect-transform.c	(this was already modified in the patches)
     tree-vectorizer.c

My original patches don't have the regression in the SPU, PowerPC ports.

So, is it important to not have the extra tree codes, but to do some more
changes not to use the tree codes?

BTW, the SPU current without patches aborts if you try to code up a rotate,
just like the current x86 with -msse5 does without my patches.  With my
patches, it looks like it generates a vector rotate:

typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));

#define SIZE 10240

#ifndef TYPE
#define TYPE int
#endif

union {
  __m128i align;
  unsigned TYPE u[SIZE];
} a, b;

void rot_num (int n)
{
  int i;

  for (i = 0; i < SIZE; i++)
    a.u[i] = (b.u[i] << n) | (b.u[i] >> ((sizeof (TYPE) * 8) - n));
}

-- 
Michael Meissner, AMD
90 Central Street, MS 83-29, Boxborough, MA, 01719, USA
michael.meissner@amd.com