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[AVX]: Add avx_ashlti3 and avx_lshlti3
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: xuepeng dot guo at intel dot com
- Date: Sat, 19 Apr 2008 15:15:59 -0700
- Subject: [AVX]: Add avx_ashlti3 and avx_lshlti3
Hi,
I am checking in this patch to add avx_ashlti3 and avx_lshlti3.
H.J.
----
2008-04-19 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (ix86_expand_sse4_unpack): Use
gen_avx_lshrti3 for AVX.
(ix86_expand_binop_imm_builtin): Use CODE_FOR_avx_ashlti3 and
CODE_FOR_avx_lshrti3 for AVX.
2008-04-19 Xuepeng Guo <xuepeng.guo@intel.com>
* config/i386/i386.md (avx_ashlti3): New.
(avx_lshlti3): Likewise.
diff -x LAST_UPDATED -x REVISION -x gcc_update -x .svn -upr -upr ../../gcc-avx/gcc/config/i386/i386.c gcc/gcc/config/i386/i386.c
--- ../../gcc-avx/gcc/config/i386/i386.c 2008-04-19 06:13:45.000000000 -0700
+++ gcc/gcc/config/i386/i386.c 2008-04-19 08:41:18.000000000 -0700
@@ -13820,11 +13820,18 @@ ix86_expand_sse4_unpack (rtx operands[2]
dest = operands[0];
if (high_p)
{
+ rtx (*lshrti3) (rtx, rtx, rtx);
+
/* Shift higher 8 bytes to lower 8 bytes. */
src = gen_reg_rtx (imode);
- emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
- gen_lowpart (TImode, operands[1]),
- GEN_INT (64)));
+ if (TARGET_AVX)
+ lshrti3 = gen_avx_lshrti3;
+ else
+ lshrti3 = gen_sse2_lshrti3;
+
+ emit_insn ((*lshrti3) (gen_lowpart (TImode, src),
+ gen_lowpart (TImode, operands[1]),
+ GEN_INT (64)));
}
else
src = operands[1];
@@ -20460,9 +20578,28 @@ ix86_expand_binop_imm_builtin (enum insn
tree arg1 = CALL_EXPR_ARG (exp, 1);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[icode].operand[1].mode;
- enum machine_mode mode1 = insn_data[icode].operand[2].mode;
+ enum machine_mode tmode;
+ enum machine_mode mode0;
+ enum machine_mode mode1;
+
+ if (TARGET_AVX)
+ switch (icode)
+ {
+ case CODE_FOR_sse2_ashlti3:
+ icode = CODE_FOR_avx_ashlti3;
+ break;
+ case CODE_FOR_sse2_lshrti3:
+ icode = CODE_FOR_avx_lshrti3;
+ break;
+ case CODE_FOR_aeskeygenassist:
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ tmode = insn_data[icode].operand[0].mode;
+ mode0 = insn_data[icode].operand[1].mode;
+ mode1 = insn_data[icode].operand[2].mode;
if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
{
diff -x LAST_UPDATED -x REVISION -x gcc_update -x .svn -upr -upr ../../gcc-avx/gcc/config/i386/i386.md gcc/gcc/config/i386/i386.md
--- ../../gcc-avx/gcc/config/i386/i386.md 2008-04-19 06:13:45.000000000 -0700
+++ gcc/gcc/config/i386/i386.md 2008-04-19 06:43:03.000000000 -0700
@@ -10941,6 +10944,18 @@
;; This pattern must be defined before *ashlti3_2 to prevent
;; combine pass from converting sse2_ashlti3 to *ashlti3_2.
+(define_insn "avx_ashlti3"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (ashift:TI (match_operand:TI 1 "register_operand" "x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
+ "TARGET_AVX"
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+ return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
+}
+ [(set_attr "type" "sseishft")
+ (set_attr "mode" "TI")])
+
(define_insn "sse2_ashlti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(ashift:TI (match_operand:TI 1 "register_operand" "0")
@@ -12632,6 +12647,18 @@
;; This pattern must be defined before *lshrti3_2 to prevent
;; combine pass from converting sse2_lshrti3 to *lshrti3_2.
+(define_insn "avx_lshrti3"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
+ "TARGET_AVX"
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+ return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
+}
+ [(set_attr "type" "sseishft")
+ (set_attr "mode" "TI")])
+
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")