[ira] SH support

[Vladimir Makarov <vmakarov at redhat dot com>]

That is what I got from Kaz Kojima.  Thanks.

2008-04-04  Kaz Kojima  <kkojima@gcc.gnu.org>

	* config/sh/sh.h (IRA_COVER_CLASSES): Define.
	* config/sh/sh.c (sh_secondary_reload): Return NO_REGS for
	null rtl.
	* config/sh/sh.md (movsicc_true+3): Check if emit returns
	a barrier.
	* final.c (update_regs_ever_live): Check null rtl.

Index: final.c
===================================================================
--- final.c	(revision 133840)
+++ final.c	(working copy)
@@ -4110,8 +4110,12 @@ update_regs_ever_live (rtx x)
 {
   int i;
   const char *fmt;
-  RTX_CODE code = GET_CODE (x);
+  RTX_CODE code;
 
+  if (x == NULL_RTX)
+    return;
+
+  code = GET_CODE (x);
   if (code == REG)
     {
       if (HARD_REGISTER_P (x))
@@ -4150,13 +4154,13 @@ rest_of_handle_final (void)
 	if (INSN_P (insn))
 	  update_regs_ever_live (PATTERN (insn));
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	if (fixed_regs [i])
+	if (fixed_regs[i])
 	  SET_HARD_REG_BIT (cfun->emit->call_used_regs, i);
 #ifdef INCOMING_REGNO
-	else if (INCOMING_REGNO (i) != i && call_used_regs [i])
+	else if (INCOMING_REGNO (i) != i && call_used_regs[i])
 	  SET_HARD_REG_BIT (cfun->emit->call_used_regs, i);
 #endif
-	else if (call_used_regs [i] &&
+	else if (call_used_regs[i] &&
 		 (df_regs_ever_live_p (i)
 #ifdef STACK_REGS
 		  || (i >= FIRST_STACK_REG && i <= LAST_STACK_REG)
@@ -4172,7 +4176,7 @@ rest_of_handle_final (void)
 	  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 	    if (TEST_HARD_REG_BIT (call_used_reg_set, i)
 		&& ! TEST_HARD_REG_BIT (cfun->emit->call_used_regs, i))
-	      fprintf (dump_file, "%s ", reg_names [i]);
+	      fprintf (dump_file, "%s ", reg_names[i]);
 	  fprintf (dump_file, "\n");
 	}
     }
Index: config/sh/sh.c
===================================================================
--- config/sh/sh.c	(revision 133840)
+++ config/sh/sh.c	(working copy)
@@ -11092,6 +11092,9 @@ enum reg_class
 sh_secondary_reload (bool in_p, rtx x, enum reg_class class,
 		     enum machine_mode mode, secondary_reload_info *sri)
 {
+  if (x == NULL_RTX)
+    return NO_REGS;
+
   if (in_p)
     {
       if (REGCLASS_HAS_FP_REG (class)
Index: config/sh/sh.h
===================================================================
--- config/sh/sh.h	(revision 133840)
+++ config/sh/sh.h	(working copy)
@@ -1494,6 +1494,20 @@ enum reg_class
 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
 
+/* The following macro defines cover classes for Integrated Register
+   Allocator.  Cover classes is a set of non-intersected register
+   classes covering all hard registers used for register allocation
+   purpose.  Any move between two registers of a cover class should be
+   cheaper than load or store of the registers.  The macro value is
+   array of register classes with LIM_REG_CLASSES used as the end
+   marker.  */
+
+#define IRA_COVER_CLASSES						     \
+{									     \
+  GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS,			     \
+  LIM_REG_CLASSES							     \
+}
+
 /* When defined, the compiler allows registers explicitly used in the
    rtl to be used as spill registers but prevents the compiler from
    extending the lifetime of these registers.  */
Index: config/sh/sh.md
===================================================================
--- config/sh/sh.md	(revision 133840)
+++ config/sh/sh.md	(working copy)
@@ -1143,7 +1143,7 @@
    (set (match_dup 4) (match_dup 5))]
   "
 {
-  rtx set1, set2;
+  rtx set1, set2, insn2;
   rtx replacements[4];
 
   /* We want to replace occurrences of operands[0] with operands[1] and
@@ -1173,7 +1173,10 @@
   extract_insn (emit_insn (set1));
   if (! constrain_operands (1))
     goto failure;
-  extract_insn (emit (set2));
+  insn2 = emit (set2);
+  if (GET_CODE (insn2) == BARRIER)
+    goto failure;
+  extract_insn (insn2);
   if (! constrain_operands (1))
     {
       rtx tmp;