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[patch] [tuples] another partial merge
- From: "Rafael Espindola" <espindola at google dot com>
- To: "Gcc Patch List" <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 20 Mar 2008 15:15:25 +0000
- Subject: [patch] [tuples] another partial merge
Tuples is now @133161
Cheers,
--
Rafael Avila de Espindola
Google Ireland Ltd.
Gordon House
Barrow Street
Dublin 4
Ireland
Registered in Dublin, Ireland
Registration Number: 368047
Property changes on: .
___________________________________________________________________
Name: svnmerge-integrated
- /trunk:1-133140
+ /trunk:1-133161
Index: config.guess
===================================================================
--- config.guess (revision 133367)
+++ config.guess (working copy)
@@ -4,7 +4,7 @@
# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
# Free Software Foundation, Inc.
-timestamp='2008-01-23'
+timestamp='2008-03-12'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1216,6 +1216,9 @@
BePC:BeOS:*:*) # BeOS running on Intel PC compatible.
echo i586-pc-beos
exit ;;
+ BePC:Haiku:*:*) # Haiku running on Intel PC compatible.
+ echo i586-pc-haiku
+ exit ;;
SX-4:SUPER-UX:*:*)
echo sx4-nec-superux${UNAME_RELEASE}
exit ;;
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi (revision 133367)
+++ gcc/doc/extend.texi (working copy)
@@ -10868,6 +10868,7 @@
* Weak Pragmas::
* Diagnostic Pragmas::
* Visibility Pragmas::
+* Push/Pop Macro Pragmas::
@end menu
@node ARM Pragmas
@@ -11064,11 +11065,11 @@
@node Structure-Packing Pragmas
@subsection Structure-Packing Pragmas
-For compatibility with Win32, GCC supports a set of @code{#pragma}
-directives which change the maximum alignment of members of structures
-(other than zero-width bitfields), unions, and classes subsequently
-defined. The @var{n} value below always is required to be a small power
-of two and specifies the new alignment in bytes.
+For compatibility with Microsoft Windows compilers, GCC supports a
+set of @code{#pragma} directives which change the maximum alignment of
+members of structures (other than zero-width bitfields), unions, and
+classes subsequently defined. The @var{n} value below always is required
+to be a small power of two and specifies the new alignment in bytes.
@enumerate
@item @code{#pragma pack(@var{n})} simply sets the new alignment.
@@ -11183,6 +11184,41 @@
@end table
+
+@node Push/Pop Macro Pragmas
+@subsection Push/Pop Macro Pragmas
+
+For compatibility with Microsoft Windows compilers, GCC supports
+@samp{#pragma push_macro(@var{"macro_name"})}
+and @samp{#pragma pop_macro(@var{"macro_name"})}.
+
+@table @code
+@item #pragma push_macro(@var{"macro_name"})
+@cindex pragma, push_macro
+This pragma saves the value of the macro named as @var{macro_name} to
+the top of the stack for this macro.
+
+@item #pragma pop_macro(@var{"macro_name"})
+@cindex pragma, pop_macro
+This pragma sets the value of the macro named as @var{macro_name} to
+the value on top of the stack for this macro. If the stack for
+@var{macro_name} is empty, the value of the macro remains unchanged.
+@end table
+
+For example:
+
+@smallexample
+#define X 1
+#pragma push_macro("X")
+#undef X
+#define X -1
+#pragma pop_macro("X")
+int x [X];
+@end smallexample
+
+In this example, the definition of X as 1 is saved by @code{#pragma
+push_macro} and restored by @code{#pragma pop_macro}.
+
@node Unnamed Fields
@section Unnamed struct/union fields within structs/unions
@cindex struct
Index: gcc/java/mangle.c
===================================================================
--- gcc/java/mangle.c (revision 133367)
+++ gcc/java/mangle.c (working copy)
@@ -239,9 +239,6 @@
void
java_mangle_decl (tree decl)
{
- if (TREE_CODE (decl) == RECORD_TYPE)
- mangle_type (decl);
-
/* A copy of the check from the beginning of lhd_set_decl_assembler_name.
Only FUNCTION_DECLs and VAR_DECLs for variables with static storage
duration need a real DECL_ASSEMBLER_NAME. */
Index: gcc/java/ChangeLog
===================================================================
--- gcc/java/ChangeLog (revision 133367)
+++ gcc/java/ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2008-03-12 Paolo Bonzini <bonzini@gnu.org>
+
+ * mangle.c (java_mangle_decl): Remove dead check.
+
2008-03-11 Paolo Bonzini <bonzini@gnu.org>
* jcf-parse.c (java_parse_file): Assert binding levels are
Index: gcc/DATESTAMP
===================================================================
--- gcc/DATESTAMP (revision 133367)
+++ gcc/DATESTAMP (working copy)
@@ -1 +1 @@
-20080312
+20080313
Index: gcc/configure
===================================================================
--- gcc/configure (revision 133367)
+++ gcc/configure (working copy)
@@ -1490,7 +1490,7 @@
use sysroot as the system root during the build
--with-sysroot=DIR Search for usr/lib, usr/include, et al, within DIR.
--with-pkgversion=PKG Use PKG in the version string in place of
- "gimple-tuples-branch merged with rev. 133140"
+ "gimple-tuples-branch merged with rev. 133161"
--with-bugurl=URL Direct users to URL to report a bug
--with-gnu-ld assume the C compiler uses GNU ld default=no
--with-libiconv-prefix[=DIR] search for libiconv in DIR/include and DIR/lib
@@ -7887,7 +7887,7 @@
*) PKGVERSION="($withval) " ;;
esac
else
- PKGVERSION="(gimple-tuples-branch merged with rev. 133140) "
+ PKGVERSION="(gimple-tuples-branch merged with rev. 133161) "
fi
Index: gcc/fold-const.c
===================================================================
--- gcc/fold-const.c (revision 133367)
+++ gcc/fold-const.c (working copy)
@@ -7927,6 +7927,26 @@
return fold_build1 (BIT_NOT_EXPR, type, fold_convert (type, tem));
}
+ /* Convert (T1)(X * Y) into (T1)X * (T1)Y if T1 is narrower than the
+ type of X and Y (integer types only). */
+ if (INTEGRAL_TYPE_P (type)
+ && TREE_CODE (op0) == MULT_EXPR
+ && INTEGRAL_TYPE_P (TREE_TYPE (op0))
+ && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (op0)))
+ {
+ /* Be careful not to introduce new overflows. */
+ tree mult_type;
+ if (TYPE_OVERFLOW_WRAPS (type))
+ mult_type = type;
+ else
+ mult_type = unsigned_type_for (type);
+
+ tem = fold_build2 (MULT_EXPR, mult_type,
+ fold_convert (mult_type, TREE_OPERAND (op0, 0)),
+ fold_convert (mult_type, TREE_OPERAND (op0, 1)));
+ return fold_convert (type, tem);
+ }
+
tem = fold_convert_const (code, type, op0);
return tem ? tem : NULL_TREE;
Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog (revision 133367)
+++ gcc/ChangeLog (working copy)
@@ -1,3 +1,68 @@
+2008-03-13 Danny Smith <dannysmith@users.sourceforge.net>
+
+ PR 35054
+ * doc/extend.texi (Structure-Packing Pragmas): Replace "Win32"
+ with the phrase "Microsoft Windows compilers".
+ (Push/Pop Macro Pragmas): New subsection. Document
+ #pragma push_macro and pragma pop_macro.
+
+2008-03-12 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/arm.c (output_move_double): Prefer LDRD to LDM.
+
+2008-03-12 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/thumb2.md: Extend peephole to cover 3-arg subs.
+ (thumb2_alusi3_short): Exclude PLUS and MINUS.
+ (thumb2_addsi_shortim): Rename ...
+ (thumb2_addsi_short): ... to this. Allow register operands.
+ (thumb2_subsi_short): New pattern.
+ (thumb2_one_cmplsi2_short,
+ thumb2_negsi2_short): New patterns and peepholes.
+
+2008-03-12 Paul Brook <paul@codesourcery.com>
+
+ gcc/
+ * config/arm/arm.c (arm_size_rtx_costs): Use ARM costs for Thumb-2.
+
+2008-03-12 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (int_cond): New code iterator.
+ (fp_cond): Ditto.
+ ("s<code>"): Macroize expander from seq, sne, sgt, sgtu, slt, sltu,
+ sge, sgeu, sle and sleu expanders usign int_cond code iterator.
+ ("s<code>"): Macroize expander from sunordered, sordered, suneq, sunge,
+ sungt, sunle, sunlt and sltgt expanders usign fp_cond code iterator.
+ ("b<code>"): Macroize expander from beq, bne, bgt, bgtu, blt, bltu,
+ bge, bgeu, ble and bleu expanders usign int_cond code iterator.
+ ("b<code>"): Macroize expander from bunordered, bordered, buneq, bunge,
+ bungt, bunle, bunlt and bltgt expanders usign fp_cond code iterator.
+
+2008-03-12 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/arm.c (use_return_insn): Use offsets->saved_regs_mask
+ instead of {arm,thumb}_compute_save_reg_mask.
+ (output_return_instruction): Ditto.
+ (thumb_unexpanded_epilogue): Ditto.
+ (thumb1_expand_prologue): Ditto.
+ (thumb1_output_function_prologue): Ditto.
+ (arm_set_return_address): Ditto.
+ (thumb_set_return_address): Ditto.
+ (arm_get_frame_offsets): Set offsets->saved_regs_mask. Push extra
+ regs to achieve stack alignment.
+ (thumb1_compute_save_reg_mask): Fix compiler warning.
+ (arm_output_epilogue): Use offsets->saved_regs_mask.
+ Adjust stack pointer by poping call clobered registers.
+ (arm_expand_prologue): Use offsets->saved_regs_mask.
+ Adjust stack pointer by pushing extra registers.
+ * gcc/config/arm.h (arm_stack_offsets): Add saved_regs_mask.
+
+2008-03-12 Paolo Bonzini <bonzini@gnu.org>
+
+ PR tree-opt/35422
+ * fold-const.c (fold_unary) <NOP_EXPR>: Distribute a narrowing
+ conversion to the operands of a multiplication.
+
2008-03-12 Richard Guenther <rguenther@suse.de>
* Makefile.in (OBJS-common): Add tree-ssa-phiprop.o
Index: gcc/testsuite/gcc.dg/vect/slp-7.c
===================================================================
--- gcc/testsuite/gcc.dg/vect/slp-7.c (revision 133367)
+++ gcc/testsuite/gcc.dg/vect/slp-7.c (working copy)
@@ -120,8 +120,9 @@
return 0;
}
-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided && vect_int_mult } } } }*/
-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { ! { vect_strided && vect_int_mult } } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { vect_unpack && vect_int_mult } } } }*/
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! { vect_unpack && vect_int_mult } } } } }*/
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target { vect_unpack && vect_int_mult } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { ! { vect_unpack && vect_int_mult } } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog (revision 133367)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -1,3 +1,10 @@
+2008-03-12 Paolo Bonzini <bonzini@gnu.org>
+
+ PR tree-opt/35422
+ * gcc.dg/vect/slp-7.c: Change target keywords required for vectorizing
+ third loop.
+ * gcc.target/i386/pr35422.c: New.
+
2008-03-11 Andrew Pinski <andrew_pinski@playstation.sony.com>
PR tree-opt/35403
Index: gcc/cp/typeck.c
===================================================================
--- gcc/cp/typeck.c (revision 133367)
+++ gcc/cp/typeck.c (working copy)
@@ -962,6 +962,8 @@
if (TREE_CODE (t1) != ARRAY_TYPE
&& TYPE_QUALS (t1) != TYPE_QUALS (t2))
return false;
+ if (TYPE_FOR_JAVA (t1) != TYPE_FOR_JAVA (t2))
+ return false;
/* Allow for two different type nodes which have essentially the same
definition. Note that we already checked for equality of the type
@@ -971,9 +973,6 @@
&& TYPE_MAIN_VARIANT (t1) == TYPE_MAIN_VARIANT (t2))
return true;
- if (TYPE_FOR_JAVA (t1) != TYPE_FOR_JAVA (t2))
- return false;
-
/* Compare the types. Break out if they could be the same. */
switch (TREE_CODE (t1))
{
Index: gcc/cp/decl.c
===================================================================
--- gcc/cp/decl.c (revision 133367)
+++ gcc/cp/decl.c (working copy)
@@ -3159,19 +3159,10 @@
tree type, decl;
if (size > 0)
type = make_signed_type (size);
- else if (size == -1)
- { /* "__java_boolean". */
- if ((TYPE_MODE (boolean_type_node)
- == smallest_mode_for_size (1, MODE_INT)))
- type = build_variant_type_copy (boolean_type_node);
- else
- /* ppc-darwin has SImode bool, make jboolean a 1-bit
- integer type without boolean semantics there. */
- type = make_unsigned_type (1);
- }
else if (size > -32)
- { /* "__java_char". */
+ { /* "__java_char" or ""__java_boolean". */
type = make_unsigned_type (-size);
+ /*if (size == -1) TREE_SET_CODE (type, BOOLEAN_TYPE);*/
}
else
{ /* "__java_float" or ""__java_double". */
Index: gcc/cp/ChangeLog
===================================================================
--- gcc/cp/ChangeLog (revision 133367)
+++ gcc/cp/ChangeLog (working copy)
@@ -1,3 +1,21 @@
+2008-03-12 Richard Guenther <rguenther@suse.de>
+
+ PR c++/35469
+ Revert:
+ 2008-02-04 Richard Guenther <rguenther@suse.de>
+
+ PR java/35035
+ * decl.c (record_builtin_java_type): Make jboolean a
+ integer type again where its mode doesn't match that of bool.
+
+ 2008-01-25 Richard Guenther <rguenther@suse.de>
+
+ PR c++/33887
+ * decl.c (record_builtin_java_type): Make __java_boolean
+ a variant of bool.
+ * typeck.c (structural_comptypes): Move TYPE_FOR_JAVA check
+ after TYPE_MAIN_VARIANT check.
+
2008-03-10 Jakub Jelinek <jakub@redhat.com>
PR c++/35328
Index: gcc/configure.ac
===================================================================
--- gcc/configure.ac (revision 133367)
+++ gcc/configure.ac (working copy)
@@ -775,7 +775,7 @@
[onestep=""])
AC_SUBST(onestep)
-ACX_PKGVERSION([gimple-tuples-branch merged with rev. 133140])
+ACX_PKGVERSION([gimple-tuples-branch merged with rev. 133161])
ACX_BUGURL([http://gcc.gnu.org/bugs.html])
# Sanity check enable_languages in case someone does not run the toplevel
Index: gcc/config/i386/i386.md
===================================================================
--- gcc/config/i386/i386.md (revision 133367)
+++ gcc/config/i386/i386.md (working copy)
@@ -515,6 +515,13 @@
[(set_attr "length" "128")
(set_attr "type" "multi")])
+;; All integer comparison codes.
+(define_code_iterator int_cond [ne eq ge gt le lt geu gtu leu ltu ])
+
+;; All floating-point comparison codes.
+(define_code_iterator fp_cond [unordered ordered
+ uneq unge ungt unle unlt ltgt ])
+
(define_code_iterator plusminus [plus minus])
;; Base name for define_insn and insn mnemonic.
@@ -13762,114 +13769,18 @@
;; to avoid partial register stalls. Otherwise do things the setcc+movzx
;; way, which can later delete the movzx if only QImode is needed.
-(define_expand "seq"
+(define_expand "s<code>"
[(set (match_operand:QI 0 "register_operand" "")
- (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ (int_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
- "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
+ "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
-(define_expand "sne"
+(define_expand "s<code>"
[(set (match_operand:QI 0 "register_operand" "")
- (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
-
-(define_expand "sgt"
- [(set (match_operand:QI 0 "register_operand" "")
- (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
-
-(define_expand "sgtu"
- [(set (match_operand:QI 0 "register_operand" "")
- (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
-
-(define_expand "slt"
- [(set (match_operand:QI 0 "register_operand" "")
- (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
-
-(define_expand "sltu"
- [(set (match_operand:QI 0 "register_operand" "")
- (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
-
-(define_expand "sge"
- [(set (match_operand:QI 0 "register_operand" "")
- (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
-
-(define_expand "sgeu"
- [(set (match_operand:QI 0 "register_operand" "")
- (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
-
-(define_expand "sle"
- [(set (match_operand:QI 0 "register_operand" "")
- (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
-
-(define_expand "sleu"
- [(set (match_operand:QI 0 "register_operand" "")
- (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
-
-(define_expand "sunordered"
- [(set (match_operand:QI 0 "register_operand" "")
- (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ (fp_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
+ "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
-(define_expand "sordered"
- [(set (match_operand:QI 0 "register_operand" "")
- (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387"
- "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
-
-(define_expand "suneq"
- [(set (match_operand:QI 0 "register_operand" "")
- (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
-
-(define_expand "sunge"
- [(set (match_operand:QI 0 "register_operand" "")
- (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
-
-(define_expand "sungt"
- [(set (match_operand:QI 0 "register_operand" "")
- (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
-
-(define_expand "sunle"
- [(set (match_operand:QI 0 "register_operand" "")
- (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
-
-(define_expand "sunlt"
- [(set (match_operand:QI 0 "register_operand" "")
- (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
-
-(define_expand "sltgt"
- [(set (match_operand:QI 0 "register_operand" "")
- (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
-
(define_insn "*setcc_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(match_operator:QI 1 "ix86_comparison_operator"
@@ -13990,150 +13901,24 @@
;; For all bCOND expanders, also expand the compare or test insn that
;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
-(define_expand "beq"
+(define_expand "b<code>"
[(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
+ (if_then_else (int_cond:CC (reg:CC FLAGS_REG)
+ (const_int 0))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
- "ix86_expand_branch (EQ, operands[0]); DONE;")
+ "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-(define_expand "bne"
+(define_expand "b<code>"
[(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
+ (if_then_else (fp_cond:CC (reg:CC FLAGS_REG)
+ (const_int 0))
+ (label_ref (match_operand 0 ""))
(pc)))]
- ""
- "ix86_expand_branch (NE, operands[0]); DONE;")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (GT, operands[0]); DONE;")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (GTU, operands[0]); DONE;")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (LT, operands[0]); DONE;")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (LTU, operands[0]); DONE;")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (GE, operands[0]); DONE;")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (GEU, operands[0]); DONE;")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (LE, operands[0]); DONE;")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "ix86_expand_branch (LEU, operands[0]); DONE;")
-
-(define_expand "bunordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
"TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
+ "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-(define_expand "bordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (ORDERED, operands[0]); DONE;")
-
-(define_expand "buneq"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNEQ, operands[0]); DONE;")
-
-(define_expand "bunge"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNGE, operands[0]); DONE;")
-
-(define_expand "bungt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNGT, operands[0]); DONE;")
-
-(define_expand "bunle"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNLE, operands[0]); DONE;")
-
-(define_expand "bunlt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (UNLT, operands[0]); DONE;")
-
-(define_expand "bltgt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (LTGT, operands[0]); DONE;")
-
(define_insn "*jcc_1"
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 133367)
+++ gcc/config/arm/arm.c (working copy)
@@ -74,7 +74,6 @@
inline static int thumb1_index_register_rtx_p (rtx, int);
static int thumb_far_jump_used_p (void);
static bool thumb_force_lr_save (void);
-static unsigned long thumb1_compute_save_reg_mask (void);
static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
static rtx emit_sfm (int, int);
static unsigned arm_size_return_regs (void);
@@ -1666,7 +1665,7 @@
&& stack_adjust == 4)))
return 0;
- saved_int_regs = arm_compute_save_reg_mask ();
+ saved_int_regs = offsets->saved_regs_mask;
/* Unfortunately, the insn
@@ -5071,13 +5070,14 @@
{
enum machine_mode mode = GET_MODE (x);
- if (TARGET_THUMB)
+ if (TARGET_THUMB1)
{
/* XXX TBD. For now, use the standard costs. */
*total = thumb1_rtx_costs (x, code, outer_code);
return true;
}
+ /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
switch (code)
{
case MEM:
@@ -9869,7 +9869,10 @@
switch (GET_CODE (XEXP (operands[1], 0)))
{
case REG:
- output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
+ if (TARGET_LDRD)
+ output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands);
+ else
+ output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
break;
case PRE_INC:
@@ -9885,7 +9888,10 @@
break;
case POST_INC:
- output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
+ if (TARGET_LDRD)
+ output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands);
+ else
+ output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
break;
case POST_DEC:
@@ -9944,8 +9950,14 @@
case LABEL_REF:
case CONST:
+ /* We might be able to use ldrd %0, %1 here. However the range is
+ different to ldr/adr, and it is broken on some ARMv7-M
+ implementations. */
output_asm_insn ("adr%?\t%0, %1", operands);
- output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
+ if (TARGET_LDRD)
+ output_asm_insn ("ldr%(d%)\t%0, [%0]", operands);
+ else
+ output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
break;
/* ??? This needs checking for thumb2. */
@@ -9959,7 +9971,7 @@
if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
{
- if (GET_CODE (otherops[2]) == CONST_INT)
+ if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
{
switch ((int) INTVAL (otherops[2]))
{
@@ -10018,6 +10030,9 @@
else
output_asm_insn ("sub%?\t%0, %1, %2", otherops);
+ if (TARGET_LDRD)
+ return "ldr%(d%)\t%0, [%0]";
+
return "ldm%(ia%)\t%0, %M0";
}
else
@@ -10046,7 +10061,10 @@
switch (GET_CODE (XEXP (operands[0], 0)))
{
case REG:
- output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
+ if (TARGET_LDRD)
+ output_asm_insn ("str%(d%)\t%1, [%m0]", operands);
+ else
+ output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
break;
case PRE_INC:
@@ -10062,7 +10080,10 @@
break;
case POST_INC:
- output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
+ if (TARGET_LDRD)
+ output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands);
+ else
+ output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
break;
case POST_DEC:
@@ -10106,7 +10127,7 @@
case PLUS:
otherops[2] = XEXP (XEXP (operands[0], 0), 1);
- if (GET_CODE (otherops[2]) == CONST_INT)
+ if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
{
switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
{
@@ -10750,7 +10771,8 @@
/* Compute a bit mask of which registers need to be
- saved on the stack for the current function. */
+ saved on the stack for the current function.
+ This is used by arm_get_frame_offsets, which may add extra registers. */
static unsigned long
arm_compute_save_reg_mask (void)
@@ -10878,7 +10900,7 @@
reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
/* Make sure the register returned by thumb_find_work_register is
not part of the return value. */
- if (reg * UNITS_PER_WORD <= arm_size_return_regs ())
+ if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ())
reg = LAST_LO_REGNUM;
if (! call_used_regs[reg])
@@ -10975,7 +10997,8 @@
return_used_this_function = 1;
- live_regs_mask = arm_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ live_regs_mask = offsets->saved_regs_mask;
if (live_regs_mask)
{
@@ -11037,7 +11060,6 @@
{
unsigned HOST_WIDE_INT stack_adjust;
- offsets = arm_get_frame_offsets ();
stack_adjust = offsets->outgoing_args - offsets->saved_regs;
gcc_assert (stack_adjust == 0 || stack_adjust == 4);
@@ -11285,7 +11307,7 @@
gcc_assert (!current_function_calls_eh_return || really_return);
offsets = arm_get_frame_offsets ();
- saved_regs_mask = arm_compute_save_reg_mask ();
+ saved_regs_mask = offsets->saved_regs_mask;
if (TARGET_IWMMXT)
lrm_count = bit_count (saved_regs_mask);
@@ -11482,8 +11504,35 @@
}
else
{
+ unsigned long count;
operands[0] = stack_pointer_rtx;
amount = offsets->outgoing_args - offsets->saved_regs;
+ /* pop call clobbered registers if it avoids a
+ separate stack adjustment. */
+ count = offsets->saved_regs - offsets->saved_args;
+ if (optimize_size
+ && count != 0
+ && !current_function_calls_eh_return
+ && bit_count(saved_regs_mask) * 4 == count
+ && !IS_INTERRUPT (func_type)
+ && !cfun->tail_call_emit)
+ {
+ unsigned long mask;
+ mask = (1 << (arm_size_return_regs() / 4)) - 1;
+ mask ^= 0xf;
+ mask &= ~saved_regs_mask;
+ reg = 0;
+ while (bit_count (mask) * 4 > amount)
+ {
+ while ((mask & (1 << reg)) == 0)
+ reg++;
+ mask &= ~(1 << reg);
+ }
+ if (bit_count (mask) * 4 == amount) {
+ amount = 0;
+ saved_regs_mask |= mask;
+ }
+ }
}
if (amount)
@@ -11954,7 +12003,8 @@
/* Calculate stack offsets. These are used to calculate register elimination
- offsets and in prologue/epilogue code. */
+ offsets and in prologue/epilogue code. Also calculates which registers
+ should be saved. */
static arm_stack_offsets *
arm_get_frame_offsets (void)
@@ -11963,7 +12013,9 @@
unsigned long func_type;
int leaf;
int saved;
+ int core_saved;
HOST_WIDE_INT frame_size;
+ int i;
offsets = &cfun->machine->stack_offsets;
@@ -11996,7 +12048,9 @@
{
unsigned int regno;
- saved = bit_count (arm_compute_save_reg_mask ()) * 4;
+ offsets->saved_regs_mask = arm_compute_save_reg_mask ();
+ core_saved = bit_count (offsets->saved_regs_mask) * 4;
+ saved = core_saved;
/* We know that SP will be doubleword aligned on entry, and we must
preserve that condition at any subroutine call. We also require the
@@ -12027,7 +12081,9 @@
}
else /* TARGET_THUMB1 */
{
- saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
+ offsets->saved_regs_mask = thumb1_compute_save_reg_mask ();
+ core_saved = bit_count (offsets->saved_regs_mask) * 4;
+ saved = core_saved;
if (TARGET_BACKTRACE)
saved += 16;
}
@@ -12047,8 +12103,40 @@
/* Ensure SFP has the correct alignment. */
if (ARM_DOUBLEWORD_ALIGN
&& (offsets->soft_frame & 7))
- offsets->soft_frame += 4;
+ {
+ offsets->soft_frame += 4;
+ /* Try to align stack by pushing an extra reg. Don't bother doing this
+ when there is a stack frame as the alignment will be rolled into
+ the normal stack adjustment. */
+ if (frame_size + current_function_outgoing_args_size == 0)
+ {
+ int reg = -1;
+ for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
+ {
+ if ((offsets->saved_regs_mask & (1 << i)) == 0)
+ {
+ reg = i;
+ break;
+ }
+ }
+
+ if (reg == -1 && arm_size_return_regs () <= 12
+ && !cfun->tail_call_emit)
+ {
+ /* Push/pop an argument register (r3) if all callee saved
+ registers are already being pushed. */
+ reg = 3;
+ }
+
+ if (reg != -1)
+ {
+ offsets->saved_regs += 4;
+ offsets->saved_regs_mask |= (1 << reg);
+ }
+ }
+ }
+
offsets->locals_base = offsets->soft_frame + frame_size;
offsets->outgoing_args = (offsets->locals_base
+ current_function_outgoing_args_size);
@@ -12303,7 +12391,8 @@
args_to_push = current_function_pretend_args_size;
/* Compute which register we will have to save onto the stack. */
- live_regs_mask = arm_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ live_regs_mask = offsets->saved_regs_mask;
ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
@@ -12456,8 +12545,28 @@
if (live_regs_mask)
{
+ saved_regs += bit_count (live_regs_mask) * 4;
+ if (optimize_size && !frame_pointer_needed
+ && saved_regs == offsets->saved_regs - offsets->saved_args)
+ {
+ /* If no coprocessor registers are being pushed and we don't have
+ to worry about a frame pointer then push extra registers to
+ create the stack frame. This is done is a way that does not
+ alter the frame layout, so is independent of the epilogue. */
+ int n;
+ int frame;
+ n = 0;
+ while (n < 8 && (live_regs_mask & (1 << n)) == 0)
+ n++;
+ frame = offsets->outgoing_args - (offsets->saved_args + saved_regs);
+ if (frame && n * 4 >= frame)
+ {
+ n = frame / 4;
+ live_regs_mask |= (1 << n) - 1;
+ saved_regs += frame;
+ }
+ }
insn = emit_multi_reg_push (live_regs_mask);
- saved_regs += bit_count (live_regs_mask) * 4;
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -12498,7 +12607,6 @@
}
}
- offsets = arm_get_frame_offsets ();
if (offsets->outgoing_args != offsets->saved_args + saved_regs)
{
/* This add can produce multiple insns for a large constant, so we
@@ -16494,6 +16602,7 @@
const char *
thumb_unexpanded_epilogue (void)
{
+ arm_stack_offsets *offsets;
int regno;
unsigned long live_regs_mask = 0;
int high_regs_pushed = 0;
@@ -16506,7 +16615,8 @@
if (IS_NAKED (arm_current_func_type ()))
return "";
- live_regs_mask = thumb1_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ live_regs_mask = offsets->saved_regs_mask;
high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
/* If we can deduce the registers used from the function's return value.
@@ -16768,7 +16878,8 @@
return;
}
- live_regs_mask = thumb1_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ live_regs_mask = offsets->saved_regs_mask;
/* Load the pic register before setting the frame pointer,
so we can use r7 as a temporary work register. */
if (flag_pic && arm_pic_register != INVALID_REGNUM)
@@ -16778,7 +16889,6 @@
emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
stack_pointer_rtx);
- offsets = arm_get_frame_offsets ();
amount = offsets->outgoing_args - offsets->saved_regs;
if (amount)
{
@@ -16940,6 +17050,7 @@
static void
thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
+ arm_stack_offsets *offsets;
unsigned long live_regs_mask = 0;
unsigned long l_mask;
unsigned high_regs_pushed = 0;
@@ -17024,7 +17135,8 @@
}
/* Get the registers we are going to push. */
- live_regs_mask = thumb1_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ live_regs_mask = offsets->saved_regs_mask;
/* Extract a mask of the ones we can give to the Thumb's push instruction. */
l_mask = live_regs_mask & 0x40ff;
/* Then count how many other high registers will need to be pushed. */
@@ -18152,7 +18264,8 @@
rtx addr;
unsigned long saved_regs;
- saved_regs = arm_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ saved_regs = offsets->saved_regs_mask;
if ((saved_regs & (1 << LR_REGNUM)) == 0)
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
@@ -18163,7 +18276,6 @@
else
{
/* LR will be the first saved register. */
- offsets = arm_get_frame_offsets ();
delta = offsets->outgoing_args - (offsets->frame + 4);
@@ -18196,11 +18308,10 @@
emit_insn (gen_rtx_USE (VOIDmode, source));
- mask = thumb1_compute_save_reg_mask ();
+ offsets = arm_get_frame_offsets ();
+ mask = offsets->saved_regs_mask;
if (mask & (1 << LR_REGNUM))
{
- offsets = arm_get_frame_offsets ();
-
limit = 1024;
/* Find the saved regs. */
if (frame_pointer_needed)
Index: gcc/config/arm/thumb2.md
===================================================================
--- gcc/config/arm/thumb2.md (revision 133367)
+++ gcc/config/arm/thumb2.md (working copy)
@@ -1002,7 +1002,10 @@
(match_operator:SI 3 "thumb_16bit_operator"
[(match_operand:SI 1 "low_register_operand" "")
(match_operand:SI 2 "low_register_operand" "")]))]
- "TARGET_THUMB2 && rtx_equal_p(operands[0], operands[1])
+ "TARGET_THUMB2
+ && (rtx_equal_p(operands[0], operands[1])
+ || GET_CODE(operands[3]) == PLUS
+ || GET_CODE(operands[3]) == MINUS)
&& peep2_regno_dead_p(0, CC_REGNUM)"
[(parallel
[(set (match_dup 0)
@@ -1019,7 +1022,9 @@
[(match_operand:SI 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "l")]))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_THUMB2 && reload_completed"
+ "TARGET_THUMB2 && reload_completed
+ && GET_CODE(operands[3]) != PLUS
+ && GET_CODE(operands[3]) != MINUS"
"%I3%!\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
@@ -1105,16 +1110,20 @@
""
)
-(define_insn "*thumb2_addsi_shortim"
+(define_insn "*thumb2_addsi_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(plus:SI (match_operand:SI 1 "low_register_operand" "l")
- (match_operand:SI 2 "const_int_operand" "IL")))
+ (match_operand:SI 2 "low_reg_or_int_operand" "lIL")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"*
HOST_WIDE_INT val;
- val = INTVAL(operands[2]);
+ if (GET_CODE (operands[2]) == CONST_INT)
+ val = INTVAL(operands[2]);
+ else
+ val = 0;
+
/* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
return \"sub%!\\t%0, %1, #%n2\";
@@ -1145,6 +1154,17 @@
(set_attr "insn" "udiv")]
)
+(define_insn "*thumb2_subsi_short"
+ [(set (match_operand:SI 0 "low_register_operand" "=l")
+ (minus:SI (match_operand:SI 1 "low_register_operand" "l")
+ (match_operand:SI 2 "low_register_operand" "l")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_THUMB2 && reload_completed"
+ "sub%!\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "2")]
+)
+
(define_insn "*thumb2_cbz"
[(set (pc) (if_then_else
(eq (match_operand:SI 0 "s_register_operand" "l,?r")
@@ -1188,3 +1208,50 @@
(const_int 2)
(const_int 8)))]
)
+
+;; 16-bit complement
+(define_peephole2
+ [(set (match_operand:SI 0 "low_register_operand" "")
+ (not:SI (match_operand:SI 1 "low_register_operand" "")))]
+ "TARGET_THUMB2
+ && peep2_regno_dead_p(0, CC_REGNUM)"
+ [(parallel
+ [(set (match_dup 0)
+ (not:SI (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+)
+
+(define_insn "*thumb2_one_cmplsi2_short"
+ [(set (match_operand:SI 0 "low_register_operand" "=l")
+ (not:SI (match_operand:SI 1 "low_register_operand" "l")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_THUMB2 && reload_completed"
+ "mvn%!\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "2")]
+)
+
+;; 16-bit negate
+(define_peephole2
+ [(set (match_operand:SI 0 "low_register_operand" "")
+ (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
+ "TARGET_THUMB2
+ && peep2_regno_dead_p(0, CC_REGNUM)"
+ [(parallel
+ [(set (match_dup 0)
+ (neg:SI (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+)
+
+(define_insn "*thumb2_negsi2_short"
+ [(set (match_operand:SI 0 "low_register_operand" "=l")
+ (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_THUMB2 && reload_completed"
+ "neg%!\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "2")]
+)
+
Index: gcc/config/arm/arm.h
===================================================================
--- gcc/config/arm/arm.h (revision 133367)
+++ gcc/config/arm/arm.h (working copy)
@@ -1538,6 +1538,7 @@
int soft_frame; /* FRAME_POINTER_REGNUM. */
int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
int outgoing_args; /* STACK_POINTER_REGNUM. */
+ unsigned int saved_regs_mask;
}
arm_stack_offsets;
Index: config.sub
===================================================================
--- config.sub (revision 133367)
+++ config.sub (working copy)
@@ -4,7 +4,7 @@
# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
# Free Software Foundation, Inc.
-timestamp='2008-01-16'
+timestamp='2008-03-08'
# This file is (in principle) common to ALL GNU software.
# The presence of a machine in this file suggests that SOME GNU software
@@ -254,8 +254,10 @@
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
+ | mips64octeon | mips64octeonel \
+ | mips64orion | mips64orionel \
+ | mips64r5900 | mips64r5900el \
| mips64vr | mips64vrel \
- | mips64orion | mips64orionel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
| mips64vr5000 | mips64vr5000el \
@@ -335,8 +337,10 @@
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
+ | mips64octeon-* | mips64octeonel-* \
+ | mips64orion-* | mips64orionel-* \
+ | mips64r5900-* | mips64r5900el-* \
| mips64vr-* | mips64vrel-* \
- | mips64orion-* | mips64orionel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
| mips64vr5000-* | mips64vr5000el-* \
@@ -364,7 +368,7 @@
| sparclite-* \
| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
| tahoe-* | thumb-* \
- | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
| tron-* \
| v850-* | v850e-* | vax-* \
| we32k-* \
Index: ChangeLog
===================================================================
--- ChangeLog (revision 133367)
+++ ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2008-03-13 Ben Elliston <bje@au.ibm.com>
+
+ * config.sub, config.guess: Update from upstream sources.
+
2008-03-06 Tom Tromey <tromey@redhat.com>
* MAINTAINERS: Update for treelang deletion.