[PATCH for H8/300]: Generation of three bit manipulation instructions in HImode for H8300H and H8S targets

["Deepen Mantri" <Deepen dot Mantri at kpitcummins dot com>]

Hi,

H8300 target's three bit manipulation instructions 'bnot', 'bset' and
'bclr' are not generated in the GCC-4.4 for the 'C' testcase provided 
below. These instructions have 2 operands and operate on a single bit
of the 8-bit destination (register/memory) operand. The first operand
specifies the bit number to be operated upon.

When the XORing, ORing and ANDing operations are to be performed on
a single bit of the destination operand, 'bnot', 'bset' and 'bclr' 
instructions can be generated respectively.  
The instruction length of these instructions is 1 byte less than the
'xor', 'or' and 'and' instructions.

Following testcase demonstrates when these instructions can be
generated.

bit_test.c
====================================================================
int main()
{
        int x = 1024 + 512 + 128 + 64;

        x ^= 1024;    ---> BNOT instead of XOR can be generated
        x ^= 64;      ---> BNOT instead of XOR can be generated
 
        x |= 1024;    ---> BSET instead of  OR can be generated
        x |= 64;      ---> BSET instead of  OR can be generated

        x &= 0xfdff;  ---> BCLR instead of AND can be generated
        x &= 0xffbf;  ---> BCLR instead of AND can be generated

        return (x);
}
====================================================================

Attached patch is written for generating these three bit manipulation
instructions when the single bit from a 'HImode'(16-bit) operand is 
needed to be operated upon.

The conditions implemented in the patch for generating these bit 
manipulation instructions are as follows:
   
  Operation                          Condition

1. XOR          If the immediate operand is exact power of 2, then
                'bnot'instruction can generated instead of 'xor'.

2. OR           If the immediate operand is exact power of 2, then
                'bset' instruction can generated instead of 'or'.
           
3. AND          If the negation of immediate operand is exact power
                of 2, then 'bclr' instruction can generated instead
                of 'and' instruction.          
                    

No new regression failures were found.  


Assembly generated before applying the patch is,

$h8300-elf-gcc -S -msx bit_test.c
====================================================================
 .file   "bit_h8.c"
        .h8300sx
        .section .text
        .align 1
        .global _main
_main:
        mov.l   er6,@-er7
        mov.l   er7,er6
        sub.l   #4,er7
        mov.w   #1728,r2
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        xor     #4,r2h        ---- (1)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        xor     #64,r2l       ---- (2)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        or      #4,r2h        ---- (3)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        or      #64,r2l       ---- (4)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        and     #253,r2h      ---- (5) 
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        and     #191,r2l      ---- (6)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        mov.w   r2,r0
        add.l   #4,er7
        rts/l   er6-er6
        .size   _main, .-_main
        .ident  "GCC: (GNU) 4.4 20080222"
        .end
==================================================================


Assembly generated after applying the patch is,

$h8300-elf-gcc -S -msx bit_test.c
==================================================================
 .file   "bit_h8.c"
        .h8300sx
        .section .text
        .align 1
        .global _main
_main:
        mov.l   er6,@-er7
        mov.l   er7,er6
        sub.l   #4,er7
        mov.w   #1728,r2
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        bnot    #2,r2h        ---- (1)
        mov.w   r2,@(-2,er6) 
        mov.w   @(-2,er6),r2
        bnot    #6,r2l        ---- (2) 
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        bset    #2,r2h        ---- (3)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        bset    #6,r2l        ---- (4)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        bclr    #1,r2h        ---- (5)
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        bclr    #6,r2l        ---- (6) 
        mov.w   r2,@(-2,er6)
        mov.w   @(-2,er6),r2
        mov.w   r2,r0
        add.l   #4,er7
        rts/l   er6-er6
        .size   _main, .-_main
        .ident  "GCC: (GNU) 4.4 20080222"
        .end
===================================================================

Patch for generating these instructions in QImode had already been
posted at the following link,
http://gcc.gnu.org/ml/gcc-patches/2007-11/msg01207.html 

Kindly let us know your comments on both the patches.

Changelog for the attached patch is as follows,

Changelog:
2008-03-07  Deepen Mantri  <Deepen.Mantri@kpitcummins.com>

	* gcc/config/h8300/h8300.c (output_logical_op): Added conditions
	for generating 'bnot', 'bset' and 'bclr' instructions in HImode.
	Also added two 'switch' cases for the same.
	(compute_logical_op_length): The instruction length of 'bnot', 
	'bset' and 'bclr' is 1 byte each.
	(print_operand): Case 'V' modified for handling HImode operands.
	Case 'W' modified for handling HImode operands.
	* gcc/testsuite/gcc.target/h8300/bnot_bset_bclr.c: New test.

Regards,
Deepen Mantri
KPIT Cummins InfoSystems Ltd.
Pune, India

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Attachment: bit_himode.patch
Description: bit_himode.patch