Re: PR 34998: Tracking of subreg liveness in global.c and ra-conflict.c

[Richard Sandiford <rsandifo at nildram dot co dot uk>]

Ian Lance Taylor <iant@google.com> writes:
> David Edelsohn <dje@watson.ibm.com> writes:
>
>> >>>>> Richard Sandiford writes:
>> 
>> > So I think the patch really does model the intended behaviour of the
>> > pseudo-register access in this case.  E.g. if we allocate an SImode
>> > pseudo FOO to two HImode registers on a 32-bit target, a set of
>> > (subreg:HI (reg:SI FOO) ...) really should clobber both of the HImode
>> > registers.  ("..." is either 0 or 2, depending on endianness.  The other
>> > value isn't valid.)
>> 
>> 	The analysis and patch seem to contradict changes made to the
>> PowerPC port in 2000:
>> 
>> http://gcc.gnu.org/ml/gcc-patches/2000-01/msg00899.html
>> http://gcc.gnu.org/ml/gcc-patches/2000-01/msg00921.html
>> 
>> A pattern implemented
>> 
>> (set (subreg:SI (reg:DI foo)) (reg:SI bar))
>> 
>> and the lifetime analysis of the period decided the pseudo was live since
>> the beginning.  Geoff Keating and RTH agreed that the SUBREG should be
>> changed to an UNSPEC specifically to express that the pattern killed the
>> entire pseudo.  Maybe the semantics have changed / been clarified in the
>> intervening time.
>
> Richard is talking about HImode => SImode.  You are talking about
> SImode => DImode, for a 32-bit target.  These are different cases,
> because multi-word subregs operate one word at a time.  Richard's
> patch effectively expands the set of the HImode subreg to clobber the
> whole SImode.  His patch would not do anything for a set of an SImode
> subreg on a 32-bit target.

Right.  To give another example of what Ian said: on a 32-bit target,
a HImode subreg of a DImode pseudo would only clobber the word that
contains the HImode value.  It would leave the other word unscathed,
as you say.

FWIW, the following part of the message addressed the "words can be
accessed individually" bit, using it as a reason why you cannot
allocate a 64-bit hard register to a 64-bit pseudo on a 32-bit target
if that pseudo has word or subword subreg references:

  The same applies to registers wider than a word.  However, my understanding
  is that CLASS_CANNOT_CHANGE_MODE must forbid cases where you might take
  word or subword subregs of supwerword hard registers, because the
  target-independent code would have expected each word of the original
  pseudo register to be independently modifiable.  E.g. if we have a
  DImode pseudo register FOO on a 32-bit target, and we have accesses
  of the form (subreg:SI (reg:DI FOO) 0) or (subreg:SI (reg:DI FOO) 4),
  we cannot allocate FOO to a 64-bit register.  Substituting a 64-bit
  register into these subregs would make one of them invalid and would
  turn the other from a half-register clobber to a full-register clobber.
  (Which subreg is which depends on endianness.)

In other words, on a 32-bit target, (subreg:SI (reg:DI FOO) 0) and
(subreg:SI (reg:DI FOO) 4) are perfectly legitimate half-register
accesses when FOO is a pseudo register.  Clobbering one does not
change the other.  But replace that 64-bit pseudo register with
a 64-bit hard register and, on a big-endian target, you make
the first subreg invalid and turn the second into a full-register
access.  C_C_C_M must therefore prevent these mode changes for
64-bit hard registers.  Doing so forces reload to replace FOO with
word or subword hard registers and reload those registers into or
out of the 64-bit hard register as necessary.

Richard