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[PATCH, i386]: Fix PR target/34673, ICE in extract_insn, at recog.c:1990
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 05 Jan 2008 12:52:47 +0100
- Subject: [PATCH, i386]: Fix PR target/34673, ICE in extract_insn, at recog.c:1990
Hello!
There was a simple inconsistency between what kind of operands insn
pattern really expects and what was generated from the expander
function. Also, VECTOR_MODE_P is not needed anymore, since we prepare
correct vector registers before generation of V4SFmode "and" pattern.
Due to recent changes to -mrecip handling, we can safely expand NR-fixed
rsqrt patterns through recently introduced (undocumnented) _sqrt_nr
builtins even without -mrecip. "Automatic" conversion to reciprocals is
still handled through ix86_builtin_reciprocal function for TARGET_RECIP
only.
Patch was bootstrapped and regression tested on x86_64-linux {, -m32}.
Patch is committed to SVN.
2008-01-05 Uros Bizjak <ubizjak@gmail.com>
PR target/34673
* config/i386/i386.c (ix86_emit_swsqrtsf): Swap input operands
in the call to gen_rtx_NE. Remove unneeded VECTOR_MODE_P check.
Update copyright year.
* config/i386/i386.md (rsqrtsf2): Enable for TARGET_SSE_MATH.
Update copyright year.
* config/i386/sse.md (rsqrtv4sf2): Ditto. Unconditionally expand
using NR fixup.
Uros.
Index: i386.md
===================================================================
--- i386.md (revision 131332)
+++ i386.md (working copy)
@@ -1,6 +1,6 @@
;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2006, 2007
+;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
@@ -16635,9 +16635,7 @@
[(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
UNSPEC_RSQRT))]
- "TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
- && flag_finite_math_only && !flag_trapping_math
- && flag_unsafe_math_optimizations"
+ "TARGET_SSE_MATH"
{
ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
DONE;
Index: sse.md
===================================================================
--- sse.md (revision 131332)
+++ sse.md (working copy)
@@ -1,5 +1,5 @@
;; GCC machine description for SSE instructions
-;; Copyright (C) 2005, 2006, 2007
+;; Copyright (C) 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
@@ -536,15 +536,10 @@
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
- "TARGET_SSE"
+ "TARGET_SSE_MATH"
{
- if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
- && flag_finite_math_only && !flag_trapping_math
- && flag_unsafe_math_optimizations)
- {
- ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
- DONE;
- }
+ ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
+ DONE;
})
(define_insn "sse_rsqrtv4sf2"
@@ -569,7 +564,7 @@
(set_attr "mode" "SF")])
(define_expand "sqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=")
+ [(set (match_operand:V4SF 0 "register_operand" "")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
"TARGET_SSE"
{
Index: i386.c
===================================================================
--- i386.c (revision 131332)
+++ i386.c (working copy)
@@ -1,6 +1,7 @@
/* Subroutines used for code generation on IA-32.
Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
- 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+ 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
This file is part of GCC.
@@ -24239,22 +24240,15 @@ void ix86_emit_swsqrtsf (rtx res, rtx a,
/* Compare a to zero. */
emit_insn (gen_rtx_SET (VOIDmode, mask,
- gen_rtx_NE (mode, a, zero)));
+ gen_rtx_NE (mode, zero, a)));
/* x0 = 1./sqrt(a) estimate */
emit_insn (gen_rtx_SET (VOIDmode, x0,
gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
UNSPEC_RSQRT)));
/* Filter out infinity. */
- if (VECTOR_MODE_P (mode))
- emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (V4SFmode, x0),
- gen_rtx_AND (mode,
- gen_lowpart (V4SFmode, x0),
- gen_lowpart (V4SFmode, mask))));
- else
- emit_insn (gen_rtx_SET (VOIDmode, x0,
- gen_rtx_AND (mode, x0, mask)));
-
+ emit_insn (gen_rtx_SET (VOIDmode, x0,
+ gen_rtx_AND (mode, x0, mask)));
/* e0 = x0 * a */
emit_insn (gen_rtx_SET (VOIDmode, e0,
gen_rtx_MULT (mode, x0, a)));