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Committed: CRIS v32 support 1/2


I've committed this; updates to the CRIS port to support CRIS v32.

The CRIS v32 variant is pipelined; each insn nominally add one
cycle (except for muls/mulu, two cycles, and for movem accesses
crossing cache-lines, one per cache-line).  There are penalties
for RaW and early use of computed address among other things;
src/sim/cris has a cycle-correct model.  It loses all addressing
modes but (mem reg) and (mem (post_inc reg)), but gains a
(non-post_inc'able) register and separate insns feeding the
"new" register in place of the most pre-v32 addressing modes -
which were actually formed by non-detachable address-prefix
insns in pre-v32.  There are improvements in pc-relative
addressing.  Most non-additive insns don't affect the carry flag
in v32.  Some insns lose a (memory) addressing mode.  It has the
same ABI as pre-v32.

What's missing in the port: insn scheduling; this requires cc0
-> cc_reg change, which I postponed awaiting df completion, and
then priorities changed.  Better stack-layout (not always
storing the return address directly on stack); that requires
changes in the middle-end where there are tests for naked RETURN
beubg the return insn, and for storing the return address in a
call-saved register (without it being removed as unused when
flag_exceptions).  The latter support is not in place, because I
believe not all required changes would be seen as appropriate
for stage 3.

There was also originally a cris-axis-elf multilib which was
source-and-binary compatible with both v10 and v32, but although
it was a great help during development, it hasn't been used for
real, could implement only a subset of the ABI and it occupied a
good part of the port, so it went.  One cris-elf multilib less.

There were no regression for cris-axis-elf nor
cris-axis-linux-gnu.  There were no real code changes in the
runtime libraries of the libraries in the gcc tree for cris-elf
(the non-v32 multilibs) or the static libraries of
cris-axis-linux-gnu, for 130927.  There were some register and
stack spill slot location rotations for the DSO's of
cris-axis-linux-gnu and there were two occurrences of juxtaposed
instructions (clear.d r11 and clear.d r12) for cris-elf
(read_sleb128 for base and v10 multilibs).  However these were
not the kind of difference that points at pessimized register
allocation (i.e. they were not pure *shifts* along
REG_ALLOC_ORDER, nor was any stack frame size increased).

A few details mentioned for posterity and full disclosure: for
crisv32-elf, there are these regressions compared to cris-elf at
130927:
FAIL: gcc.dg/pr30643.c scan-assembler-not undefined
FAIL: g++.old-deja/g++.abi/vtable2.C (test for excess errors)
FAIL: 27_io/basic_ostream/inserters_arithmetic/char/1.cc execution test

For the latter two, these messages were in the .logs,
respectively (line-wrapped):

/tmp/ccblpWw2.s: Assembler messages:
/tmp/ccblpWw2.s:1095: Error: symbol definition loop encountered at `_S3_s3'
/tmp/ccblpWw2.s:1095: Error: symbol definition loop encountered at `_S4_s1'

assertion "os && os.str() == tc.result" failed: file
"/home/hp/combn/combined/libstdc++-v3/testsuite/27_io/basic_ostream
/inserters_arithmetic/char/1.cc", line 168, function: void test01()

For 130398, 22_locale/money_get/get/char/5.cc failed for
crisv32-elf with an illegal memory access which I've tracked to
a miscompiled _vfprintf_r in newlib.  On inspection, it's
apparently miscompiled for pre-v32 too, but masked with a 0 at
the critical stack-location.  That test looks similar to the
1.cc test above.  Film at 11.

These are the regressions for crisv32-axis-linux-gnu compared to
cris-axis-linux-gnu:
FAIL: gcc.dg/pr30643.c scan-assembler-not undefined
FAIL: g++.old-deja/g++.abi/vtable2.C (test for excess errors)
WARNING: program timed out.
FAIL: tr1/5_numerical_facilities/special_functions/17_hyperg/check_value.cc execution test

The error for vtable2.C is the same.  No further hints in the
log for the libstdc++ failure.

Part 1, testsuite and libraries:

libgcc:
	* config.host (crisv32-*-elf, crisv32-*-none): New, same as
	cris-*-elf and cris-*-none.
	(crisv32-*-linux*): Similar, as cris-*-linux*.

libstdc++-v3;
	* configure.host (try_cpu settings): Set try_cpu=cris for crisv32.
	* config/cpu/cris/atomicity.h (__exchange_and_add)
	[__CRIS_arch_version >= 32]: Add support for CRIS v32.

gcc/testsuite:
	* gcc.target/cris/peep2-xsrand.c, gcc.target/cris/asmreg-1.c,
	gcc.target/cris/peep2-andu1.c, gcc.target/cris/peep2-xsrand2.c,
	gcc.target/cris/20011127-1.c: Drop redundant target-specifier.
	* gcc.target/cris/peep2-andu2.c: Ditto.  Make dg-do assemble and
	add -save-temps.
	* gcc.target/cris/torture/cris-torture.exp,
	gcc.target/cris/cris.exp: Run for crisv32-*-* too.
	* gcc.target/cris/builtin_ctz_v3.c,
	gcc.target/cris/builtin_ctz_v8.c,
	gcc.target/cris/builtin_clz_v0.c,
	gcc.target/cris/builtin_clz_v3.c,
	gcc.target/cris/builtin_bswap_v3.c,
	gcc.target/cris/builtin_bswap_v8.c, gcc.dg/sibcall-4.c,
	gcc.dg/pr19340.c, gcc.dg/20020919-1.c, gcc.dg/pr31866.c,
	gcc.dg/torture/cris-asm-mof-1.c, gcc.dg/torture/cris-volatile-1.c,
	gcc.dg/weak/typeof-2.c, gcc.dg/tree-ssa/loop-1.c,
	gcc.dg/tree-ssa/20040204-1.c, gcc.dg/sibcall-3.c,
	lib/target-supports.exp: Adjust for crisv32-*-*.

Index: libstdc++-v3/config/cpu/cris/atomicity.h
===================================================================
--- libstdc++-v3/config/cpu/cris/atomicity.h	(revision 130951)
+++ libstdc++-v3/config/cpu/cris/atomicity.h	(working copy)
@@ -37,7 +37,20 @@ _GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx)
     int __tmp;
     _Atomic_word __result;
 
-#if (__CRIS_arch_version >= 10)
+#if (__CRIS_arch_version >= 32)
+  __asm__ __volatile__ (" clearf p	       \n"
+		       "0:		       \n"
+		       " move.d %4,%2	       \n"
+		       " move.d [%3],%0	       \n"
+		       " add.d %0,%2	       \n"
+		       " ax		       \n"
+		       " move.d %2,[%3]	       \n"
+		       " bcs 0b		       \n"
+		       " clearf p	       \n"
+		       :  "=&r" (__result), "=Q" (*__mem), "=&r" (__tmp)
+		       : "r" (__mem), "g" (__val), "Q" (*__mem)
+		       : "memory");
+#elif (__CRIS_arch_version >= 10)
     __asm__ __volatile__ (" clearf		\n"
 			"0:			\n"
 			" move.d %4,%2		\n"

Index: libgcc/config.host
===================================================================
--- libgcc/config.host	(revision 130951)
+++ libgcc/config.host	(working copy)
@@ -264,10 +264,10 @@ c4x-* | tic4x-*)
 	;;
 cris-*-aout)
 	;;
-cris-*-elf | cris-*-none)
+crisv32-*-elf | crisv32-*-none | cris-*-elf | cris-*-none)
 	extra_parts="crtbegin.o crtend.o"
 	;;
-cris-*-linux*)
+cris-*-linux* | crisv32-*-linux*)
 	;;
 crx-*-elf)
 	;;

Index: gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we don't use the swap insn for ctz by checking
    assembler output.  The swap instruction was implemented in v8.  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v3" } */
 /* { dg-final { scan-assembler-not "\[ \t\]swapwbr\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we use the swap insn for ctz by checking assembler output.
    The swap instruction was implemented in v8.  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v8" } */
 /* { dg-final { scan-assembler "\[ \t\]swapwbr\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/peep2-xsrand.c
===================================================================
--- gcc/testsuite/gcc.target/cris/peep2-xsrand.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/peep2-xsrand.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile } */
 /* { dg-final { scan-assembler "and.w " } } */
 /* { dg-final { scan-assembler "and.b " } } */
 /* { dg-final { scan-assembler-not "and.d" } } */
Index: gcc/testsuite/gcc.target/cris/cris.exp
===================================================================
--- gcc/testsuite/gcc.target/cris/cris.exp	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/cris.exp	(working copy)
@@ -18,7 +18,7 @@
 # looping over tests.
 
 # Exit immediately if this isn't a CRIS target.
-if ![istarget cris-*-*] then {
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
   return
 }
 
Index: gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we don't use the swap insn for bswap by checking assembler 
    output.  The swap instruction was added in v8.  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v3" } */
 /* { dg-final { scan-assembler-not "\[ \t\]swapwb\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/asmreg-1.c
===================================================================
--- gcc/testsuite/gcc.target/cris/asmreg-1.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/asmreg-1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile } */
 /* { dg-options "-O2" } */
 /* { dg-final { scan-assembler "\\\.ifnc \\\$r9-\\\$r10-\\\$r11-\\\$r12" } } */
 
Index: gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we use the swap insn for bswap by checking assembler
    output.  The swap instruction was added in v8.  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v8" } */
 /* { dg-final { scan-assembler "\[ \t\]swapwb\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/peep2-andu1.c
===================================================================
--- gcc/testsuite/gcc.target/cris/peep2-andu1.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/peep2-andu1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile } */
 /* { dg-final { scan-assembler-not "and.d " } } */
 /* { dg-final { scan-assembler-not "move.d " } } */
 /* { dg-final { scan-assembler "cLear.b" } } */
Index: gcc/testsuite/gcc.target/cris/peep2-andu2.c
===================================================================
--- gcc/testsuite/gcc.target/cris/peep2-andu2.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/peep2-andu2.c	(working copy)
@@ -1,11 +1,11 @@
-/* { dg-do compile { target cris-*-* } } */
-/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$r" } } */
-/* { dg-final { scan-assembler "and.w 2047,\\\$r" } } */
-/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$r" } } */
-/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$r" } } */
-/* { dg-final { scan-assembler "and.b 95,\\\$r" } } */
-/* { dg-final { scan-assembler "andq -2,\\\$r" } } */
-/* { dg-options "-O2" } */
+/* { dg-do assemble } */
+/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "and.w 2047,\\\$" } } */
+/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "and.b 95,\\\$" } } */
+/* { dg-final { scan-assembler "andq -2,\\\$" } } */
+/* { dg-options "-O2 -save-temps" } */
 
 /* Test the "andu" peephole2 trivially, register operand.  */
 
Index: gcc/testsuite/gcc.target/cris/torture/cris-torture.exp
===================================================================
--- gcc/testsuite/gcc.target/cris/torture/cris-torture.exp	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/torture/cris-torture.exp	(working copy)
@@ -18,7 +18,7 @@
 # optimization options.
 
 # Exit immediately if this isn't a CRIS target.
-if ![istarget cris-*-*] then {
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
   return
 }
 
Index: gcc/testsuite/gcc.target/cris/builtin_clz_v0.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_clz_v0.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_clz_v0.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we don't use the lz insn for clz by checking assembler output.
    The lz insn was implemented in CRIS v3 (ETRAX 4).  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v0" } */
 /* { dg-final { scan-assembler-not "\[ \t\]lz\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/builtin_clz_v3.c
===================================================================
--- gcc/testsuite/gcc.target/cris/builtin_clz_v3.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/builtin_clz_v3.c	(working copy)
@@ -1,7 +1,7 @@
 /* Check that we use the lz insn for clz by checking assembler output.
    The lz insn was implemented in CRIS v3 (ETRAX 4).  */
 /* { dg-do compile } */
-/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v3" } */
 /* { dg-final { scan-assembler "\[ \t\]lz\[ \t\]" } } */
 
Index: gcc/testsuite/gcc.target/cris/peep2-xsrand2.c
===================================================================
--- gcc/testsuite/gcc.target/cris/peep2-xsrand2.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/peep2-xsrand2.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile } */
 /* { dg-final { scan-assembler "and.w -137," } } */
 /* { dg-final { scan-assembler "and.b -64," } } */
 /* { dg-final { scan-assembler "and.w -139," } } */
Index: gcc/testsuite/gcc.target/cris/20011127-1.c
===================================================================
--- gcc/testsuite/gcc.target/cris/20011127-1.c	(revision 130951)
+++ gcc/testsuite/gcc.target/cris/20011127-1.c	(working copy)
@@ -3,9 +3,9 @@
 
    Making sure that invalid asm operand modifiers don't cause an ICE.  */
 
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile } */
 /* { dg-options "-O2" } */
-/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target cris-*-* } 0 } */
+/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target *-*-* } 0 } */
 
 void
 foo (void)
Index: gcc/testsuite/gcc.dg/sibcall-4.c
===================================================================
--- gcc/testsuite/gcc.dg/sibcall-4.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/sibcall-4.c	(working copy)
@@ -5,7 +5,7 @@
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
+/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* { dg-options "-O2 -foptimize-sibling-calls" } */
Index: gcc/testsuite/gcc.dg/pr19340.c
===================================================================
--- gcc/testsuite/gcc.dg/pr19340.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/pr19340.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fschedule-insns2 -fsched2-use-traces" } */
-/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* fido-*-* m68k-*-* m32c-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* m32c-*-* } { "*" } { "" } } */
 
 extern double f (double x);
 
Index: gcc/testsuite/gcc.dg/20020919-1.c
===================================================================
--- gcc/testsuite/gcc.dg/20020919-1.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/20020919-1.c	(working copy)
@@ -8,7 +8,7 @@
    You must be this tall ---> fit two long longs in asm-declared registers
    to enter this amusement.  */
 
-/* { dg-do compile { target alpha-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
+/* { dg-do compile { target alpha-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
 /* { dg-options "-O2" } */
 
 /* Constructed examples; input/output (same register), output, input, and
Index: gcc/testsuite/gcc.dg/pr31866.c
===================================================================
--- gcc/testsuite/gcc.dg/pr31866.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/pr31866.c	(working copy)
@@ -1,5 +1,5 @@
 /* PR tree-optimization/31866 */
-/* { dg-do compile { target alpha-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
+/* { dg-do compile { target alpha-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
 /* { dg-options "-O2" } */
 
 #if defined (__alpha__)
Index: gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c	(working copy)
@@ -1,5 +1,5 @@
-/* { dg-do compile { target cris-*-* } } */
-/* { dg-skip-if "" { cris-*-* } { "-march*" } { "" } } */
+/* { dg-do compile { target cris-*-* crisv32-*-* } } */
+/* { dg-skip-if "" { cris*-*-* } { "-march*" } { "" } } */
 /* { dg-options "-O2 -march=v10" } */
 /* { dg-final { scan-assembler "in-asm: .mof" } } */
 /* { dg-final { scan-assembler "out-asm: .mof" } } */
Index: gcc/testsuite/gcc.dg/torture/cris-volatile-1.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/cris-volatile-1.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/torture/cris-volatile-1.c	(working copy)
@@ -2,7 +2,7 @@
    Check that size-optimizations for move insns (specifically peephole
    optimizations) aren't applied to volatile objects in the CRIS port.
    Origin: Hans-Peter Nilsson.  */
-/* { dg-do compile { target cris-*-* } } */
+/* { dg-do compile { target cris-*-* crisv32-*-* } } */
 /* { dg-final { scan-assembler-not {movu\...\[} } } */
 /* { dg-final { scan-assembler-not {move\.[^d].\[} } } */
 /* { dg-final { scan-assembler-not {and\.[^d].\[} } } */
Index: gcc/testsuite/gcc.dg/weak/typeof-2.c
===================================================================
--- gcc/testsuite/gcc.dg/weak/typeof-2.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/weak/typeof-2.c	(working copy)
@@ -39,6 +39,7 @@ int bar3 (int x)
 // { dg-final { if [string match s390*-*-* $target_triplet ] {return} } }
 // Likewise for CRIS targets.
 // { dg-final { if [string match cris-*-* $target_triplet ] {return} } }
+// { dg-final { if [string match crisv32-*-* $target_triplet ] {return} } }
 // Likewise for m68k targets.
 // { dg-final { if [string match fido-*-* $target_triplet ] {return} } }
 // { dg-final { if [string match m68k-*-* $target_triplet ] {return} } }
Index: gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/loop-1.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/tree-ssa/loop-1.c	(working copy)
@@ -39,7 +39,7 @@ void xxx(void)
 /* CRIS keeps the address in a register.  */
 /* m68k sometimes puts the address in a register, depending on CPU and PIC.  */
 
-/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* fido-*-* m68k-*-* } } } */
+/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* } } } */
 /* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
 /* { dg-final { scan-assembler-times "= foo"  5 { target ia64*-*-* } } } */
 /* { dg-final { scan-assembler-times "jsr|bsrf|blink\ttr?,r18"  5 { target sh*-*-* } } } */
Index: gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c	(working copy)
@@ -33,5 +33,5 @@ void test55 (int x, int y)
    that the && should be emitted (based on BRANCH_COST).  Fix this
    by teaching dom to look through && and register all components
    as true.  */
-/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "powerpc*-*-* cris-*-* mmix-*-* mips*-*-*" } } } } */
+/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "powerpc*-*-* cris-*-* crisv32-*-* mmix-*-* mips*-*-*" } } } } */
 /* { dg-final { cleanup-tree-dump "optimized" } } */
Index: gcc/testsuite/gcc.dg/sibcall-3.c
===================================================================
--- gcc/testsuite/gcc.dg/sibcall-3.c	(revision 130951)
+++ gcc/testsuite/gcc.dg/sibcall-3.c	(working copy)
@@ -5,7 +5,7 @@
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
+/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* { dg-options "-O2 -foptimize-sibling-calls" } */
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp	(revision 130951)
+++ gcc/testsuite/lib/target-supports.exp	(working copy)
@@ -421,6 +421,7 @@ proc check_profiling_available { test_wh
 	     || [istarget strongarm*-*-elf]
 	     || [istarget xscale*-*-elf]
 	     || [istarget cris-*-*]
+	     || [istarget crisv32-*-*]
 	     || [istarget fido-*-elf]
 	     || [istarget h8300-*-*]
 	     || [istarget m32c-*-elf]

brgds, H-P


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