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[PATCH] i386: Fix PR target/29493 and PR target/29473 -masm=intel problems
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 22 Oct 2007 00:00:22 +0200
- Subject: [PATCH] i386: Fix PR target/29493 and PR target/29473 -masm=intel problems
This patch fixes a number of problems with the -masm=intel option. The
fixes can be divided into three categories:
1. PR 29493 which is about emitting register prefixes in Intel syntax.
2. PR 29473 which is about missing implementation of RIP relative addressing
in Intel syntax and the "rep ret" bug.
3. Several places with missing or broken Intel syntax support.
Intel syntax is messy when it comes to displacement+register addressing
and rather than duplicating the code to output it for the RIP relative case,
I decided to hook into the existing code by setting 'base' to pc_rtx and
having print_reg() accept it.
Bootstrapped and tested on x86_64-unknown-linux-gnu with no new failures.
I also tested bootstrap with BOOT_CFLAGS='-O2 -g -fomit-frame-pointer
-masm=intel'. To to that, I used an additional patch to longlong.h to
disable the inline asm:
Index: gcc/longlong.h
===================================================================
--- gcc/longlong.h (revision 129233)
+++ gcc/longlong.h (working copy)
@@ -318,6 +318,7 @@ UDItype __umulsidi3 (USItype, USItype);
#endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
+#if 0
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl %5,%1\n\tadcl %3,%0" \
: "=r" ((USItype) (sh)), \
@@ -347,6 +348,7 @@ UDItype __umulsidi3 (USItype, USItype);
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"rm" ((USItype) (dv)))
+#endif /* 0 */
#define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
#define UMUL_TIME 40
@@ -354,6 +356,7 @@ UDItype __umulsidi3 (USItype, USItype);
#endif /* 80x86 */
#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
+#if 0
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addq %5,%1\n\tadcq %3,%0" \
: "=r" ((UDItype) (sh)), \
@@ -383,6 +386,7 @@ UDItype __umulsidi3 (USItype, USItype);
: "0" ((UDItype) (n0)), \
"1" ((UDItype) (n1)), \
"rm" ((UDItype) (dv)))
+#endif /* 0 */
#define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
#define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
#define UMUL_TIME 40
I think longlong.h needs to be checked to see if we can do without the
inline asm, so I didn't try to fix it yet. In particular, the add_ssaaaa()
and sub_ddmmss() macros ought to be fine with the C implementation after the
patches that went in for PR 30315. I'll do this part separately.
Finally, I ran the testsuite with -masm=intel. There are 13596 tests
that used to fail and now work. There are a few testcases where the failure
changes: gcc.c-torture/compile/20050520-1.c and
gcc.c-torture/execute/20030914-2.c now fail to compile at a few more
optimization levels where gas rejects the asm output. Similarly,
gcc.target/i386/pr13685.c and g++.old-deja/g++.pt/static7.C now fail to
assemble. Gas mistakes a variable name for a keyword. I'm not sure if it's
just gas being stupid or a an actual limitation of Intel syntax. Finally,
gcc.target/i386/pr33552.c now compiles but instead fails the execution test
because of inline asm where the operand order isn't correct for Intel
syntax. I suppose that could be fixed.
2007-10-21 Rask Ingemann Lambertsen <rask@sygehus.dk>
PR target/29473
PR target/29493
* config/i386/i386.c (output_pic_addr_const): Support Intel asm syntax.
(print_reg): Print register prefix only with AT&T asm syntax.
Support pc_rtx for RIP register.
(print_operand_address): Use print_reg()'s pc_rtx support for RIP
relative addressing. Always print segment register prefix with AT&T
asm syntax and never with Intel asm syntax.
(print_operand): Suppress 'XXX PTR' prefix for BLKmode operands.
Fix prefix for 16-byte XFmode operands.
(output_addr_const_extra): Support Intel asm syntax.
(x86_file_start): Don't use register prefix with Intel asm syntax.
* config/i386/i386.md ("*zero_extendqihi2_movzbl"): Fix typo.
("return_internal_long"): Fix Intel asm syntax output.
("set_got_rex64"): Support Intel asm syntax.
("set_rip_rex64"): Likewise.
("set_got_offset_rex64"): Likewise.
("*sibcall_1_rex64_v"): Print register prefix only with AT&T asm
syntax.
("*tls_global_dynamic_64"): Likewise.
("*tls_local_dynamic_base_64"): Likewise.
("*load_tp_si")("*load_tp_di"): Likewise.
("*add_tp_si")("*add_tp_di"): Likewise.
("*tls_dynamic_lea_64"): Likewise.
("*sibcall_value_1_rex64_v"): Likewise.
("stack_tls_protect_set_si"): Likewise.
("stack_tls_protect_set_di"): Likewise.
("stack_tls_protect_test_si"): Likewise.
("stack_tls_protect_test_di"): Likewise.
* config/i386/mmx.md ("*mov<mode>_internal_rex64"): Fix Intel asm
syntax output.
("*movv2sf_internal_rex64"): Likewise.
* config/i386/cpuid.h (__cpuid): Support Intel asm syntax.
(__get_cpuid_max): Likewise.
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c (revision 129233)
+++ gcc/config/i386/i386.c (working copy)
@@ -8186,7 +8186,8 @@ output_pic_addr_const (FILE *file, rtx x
fputs ("@PLTOFF", file);
break;
case UNSPEC_GOTPCREL:
- fputs ("@GOTPCREL(%rip)", file);
+ fputs (ASSEMBLER_DIALECT == ASM_ATT ?
+ "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
break;
case UNSPEC_GOTTPOFF:
/* FIXME: This might be @TPOFF in Sun ld too. */
@@ -8206,7 +8207,8 @@ output_pic_addr_const (FILE *file, rtx x
break;
case UNSPEC_GOTNTPOFF:
if (TARGET_64BIT)
- fputs ("@GOTTPOFF(%rip)", file);
+ fputs (ASSEMBLER_DIALECT == ASM_ATT ?
+ "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
else
fputs ("@GOTNTPOFF", file);
break;
@@ -8532,15 +8534,23 @@ put_condition_code (enum rtx_code code,
void
print_reg (rtx x, int code, FILE *file)
{
- gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
- && REGNO (x) != FRAME_POINTER_REGNUM
- && REGNO (x) != FLAGS_REG
- && REGNO (x) != FPSR_REG
- && REGNO (x) != FPCR_REG);
+ gcc_assert (x == pc_rtx
+ || (REGNO (x) != ARG_POINTER_REGNUM
+ && REGNO (x) != FRAME_POINTER_REGNUM
+ && REGNO (x) != FLAGS_REG
+ && REGNO (x) != FPSR_REG
+ && REGNO (x) != FPCR_REG));
- if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
+ if (ASSEMBLER_DIALECT == ASM_ATT)
putc ('%', file);
+ if (x == pc_rtx)
+ {
+ gcc_assert (TARGET_64BIT);
+ fputs ("rip", file);
+ return;
+ }
+
if (code == 'w' || MMX_REG_P (x))
code = 2;
else if (code == 'b')
@@ -9037,8 +9047,9 @@ print_operand (FILE *file, rtx x, int co
else if (MEM_P (x))
{
- /* No `byte ptr' prefix for call instructions. */
- if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
+ /* No `byte ptr' prefix for call instructions or BLKmode operands. */
+ if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
+ && GET_MODE (x) != BLKmode)
{
const char * size;
switch (GET_MODE_SIZE (GET_MODE (x)))
@@ -9048,7 +9059,12 @@ print_operand (FILE *file, rtx x, int co
case 4: size = "DWORD"; break;
case 8: size = "QWORD"; break;
case 12: size = "XWORD"; break;
- case 16: size = "XMMWORD"; break;
+ case 16:
+ if (GET_MODE (x) == XFmode)
+ size = "XWORD";
+ else
+ size = "XMMWORD";
+ break;
default:
gcc_unreachable ();
}
@@ -9166,7 +9182,7 @@ print_operand_address (FILE *file, rtx a
break;
case SEG_FS:
case SEG_GS:
- if (USER_LABEL_PREFIX[0] == 0)
+ if (ASSEMBLER_DIALECT == ASM_ATT)
putc ('%', file);
fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
break;
@@ -9174,6 +9190,21 @@ print_operand_address (FILE *file, rtx a
gcc_unreachable ();
}
+ /* Use one byte shorter RIP relative addressing for 64bit mode. */
+ if (TARGET_64BIT && !base && !index)
+ {
+ rtx symbol = disp;
+
+ if (GET_CODE (disp) == CONST
+ && GET_CODE (XEXP (disp, 0)) == PLUS
+ && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
+ symbol = XEXP (XEXP (disp, 0), 0);
+
+ if (GET_CODE (symbol) == LABEL_REF
+ || (GET_CODE (symbol) == SYMBOL_REF
+ && SYMBOL_REF_TLS_MODEL (symbol) == 0))
+ base = pc_rtx;
+ }
if (!base && !index)
{
/* Displacement only requires special attention. */
@@ -9181,30 +9212,13 @@ print_operand_address (FILE *file, rtx a
if (CONST_INT_P (disp))
{
if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
- {
- if (USER_LABEL_PREFIX[0] == 0)
- putc ('%', file);
- fputs ("ds:", file);
- }
+ fputs ("ds:", file);
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
}
else if (flag_pic)
output_pic_addr_const (file, disp, 0);
else
output_addr_const (file, disp);
-
- /* Use one byte shorter RIP relative addressing for 64bit mode. */
- if (TARGET_64BIT)
- {
- if (GET_CODE (disp) == CONST
- && GET_CODE (XEXP (disp, 0)) == PLUS
- && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
- disp = XEXP (XEXP (disp, 0), 0);
- if (GET_CODE (disp) == LABEL_REF
- || (GET_CODE (disp) == SYMBOL_REF
- && SYMBOL_REF_TLS_MODEL (disp) == 0))
- fputs ("(%rip)", file);
- }
}
else
{
@@ -9320,7 +9334,8 @@ output_addr_const_extra (FILE *file, rtx
case UNSPEC_GOTNTPOFF:
output_addr_const (file, op);
if (TARGET_64BIT)
- fputs ("@GOTTPOFF(%rip)", file);
+ fputs (ASSEMBLER_DIALECT == ASM_ATT ?
+ "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
else
fputs ("@GOTNTPOFF", file);
break;
@@ -22736,7 +22751,7 @@ x86_file_start (void)
if (X86_FILE_START_FLTUSED)
fputs ("\t.global\t__fltused\n", asm_out_file);
if (ix86_asm_dialect == ASM_INTEL)
- fputs ("\t.intel_syntax\n", asm_out_file);
+ fputs ("\t.intel_syntax noprefix\n", asm_out_file);
}
int
Index: gcc/config/i386/i386.md
===================================================================
--- gcc/config/i386/i386.md (revision 129233)
+++ gcc/config/i386/i386.md (working copy)
@@ -3434,7 +3434,7 @@
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
- "movz{bl|x}\t{%1, %k0|%k0, %k1}"
+ "movz{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
@@ -14902,7 +14902,7 @@
[(call (mem:QI (reg:DI R11_REG))
(match_operand 0 "" ""))]
"SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t*%%r11"
+ "jmp\t{*%%}r11"
[(set_attr "type" "call")])
@@ -15032,7 +15032,7 @@
[(return)
(unspec [(const_int 0)] UNSPEC_REP)]
"reload_completed"
- "rep{\;| }ret"
+ "rep\;ret"
[(set_attr "length" "1")
(set_attr "length_immediate" "0")
(set_attr "prefix_rep" "1")
@@ -15111,7 +15111,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
"TARGET_64BIT"
- "lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
+ "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
[(set_attr "type" "lea")
(set_attr "length" "6")])
@@ -15119,7 +15119,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
"TARGET_64BIT"
- "lea{q}\t%l1(%%rip), %0"
+ "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
(set_attr "length" "6")])
@@ -15127,7 +15127,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
"TARGET_64BIT"
- "movabs{q}\t$_GLOBAL_OFFSET_TABLE_-%l1, %0"
+ "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
(set_attr "length" "11")])
@@ -15748,7 +15748,7 @@
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
- ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
+ ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\;.word\t0x6666\;rex64\;call\t%P2"
[(set_attr "type" "multi")
(set_attr "length" "16")])
@@ -15826,7 +15826,7 @@
(match_operand:DI 2 "" "")))
(unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
"TARGET_64BIT"
- "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
+ "lea{q}\t{%&@TLSLD(%%rip), %%rdi|rdi, %&@TLSLD[rip]}\;call\t%P1"
[(set_attr "type" "multi")
(set_attr "length" "12")])
@@ -15876,7 +15876,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_TP))]
"!TARGET_64BIT"
- "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
+ "mov{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
(set_attr "length" "7")
@@ -15889,7 +15889,7 @@
(match_operand:SI 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
- "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
+ "add{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")
(set_attr "length" "7")
@@ -15900,7 +15900,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] UNSPEC_TP))]
"TARGET_64BIT"
- "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+ "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
(set_attr "length" "7")
@@ -15913,7 +15913,7 @@
(match_operand:DI 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
+ "add{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")
(set_attr "length" "7")
@@ -16009,7 +16009,7 @@
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLSDESC))]
"TARGET_64BIT && TARGET_GNU2_TLS"
- "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[%%rip]}"
+ "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
[(set_attr "type" "lea")
(set_attr "mode" "DI")
(set_attr "length" "7")
@@ -21255,7 +21255,7 @@
(call (mem:QI (reg:DI R11_REG))
(match_operand:DI 1 "" "")))]
"SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t*%%r11"
+ "jmp\t{*%%}r11"
[(set_attr "type" "callv")])
;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
@@ -21463,7 +21463,7 @@
(set (match_scratch:SI 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
""
- "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
+ "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_set_di"
@@ -21477,9 +21477,9 @@
system call would not have to trash the userspace segment register,
which would be expensive */
if (ix86_cmodel != CM_KERNEL)
- return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+ return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
else
- return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR %%gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
+ return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
}
[(set_attr "type" "multi")])
@@ -21538,7 +21538,7 @@
UNSPEC_SP_TLS_TEST))
(clobber (match_scratch:SI 3 "=r"))]
""
- "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
+ "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR gs:%P2}"
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_test_di"
@@ -21553,9 +21553,9 @@
system call would not have to trash the userspace segment register,
which would be expensive */
if (ix86_cmodel != CM_KERNEL)
- return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}";
+ return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR fs:%P2}";
else
- return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR %%gs:%P2}";
+ return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR gs:%P2}";
}
[(set_attr "type" "multi")])
Index: gcc/config/i386/mmx.md
===================================================================
--- gcc/config/i386/mmx.md (revision 129233)
+++ gcc/config/i386/mmx.md (working copy)
@@ -69,8 +69,8 @@
"TARGET_64BIT && TARGET_MMX
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
+ mov{q}\t{%1, %0|%0, %1}
+ mov{q}\t{%1, %0|%0, %1}
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
@@ -128,8 +128,8 @@
"TARGET_64BIT && TARGET_MMX
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
+ mov{q}\t{%1, %0|%0, %1}
+ mov{q}\t{%1, %0|%0, %1}
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
Index: gcc/config/i386/cpuid.h
===================================================================
--- gcc/config/i386/cpuid.h (revision 129233)
+++ gcc/config/i386/cpuid.h (working copy)
@@ -62,9 +62,9 @@
#if defined(__i386__) && defined(__PIC__)
/* %ebx may be the PIC register. */
#define __cpuid(level, a, b, c, d) \
- __asm__ ("xchgl\t%%ebx, %1\n\t" \
+ __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
"cpuid\n\t" \
- "xchgl\t%%ebx, %1\n\t" \
+ "xchg{l}\t{%%}ebx, %1\n\t" \
: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
: "0" (level))
#else
@@ -88,16 +88,16 @@ __get_cpuid_max (unsigned int __ext, uns
#ifndef __x86_64__
/* See if we can use cpuid. On AMD64 we always can. */
- __asm__ ("pushfl\n\t"
- "pushfl\n\t"
- "popl\t%0\n\t"
- "movl\t%0, %1\n\t"
- "xorl\t%2, %0\n\t"
- "pushl\t%0\n\t"
- "popfl\n\t"
- "pushfl\n\t"
- "popl\t%0\n\t"
- "popfl\n\t"
+ __asm__ ("pushf{l|d}\n\t"
+ "pushf{l|d}\n\t"
+ "pop{l}\t%0\n\t"
+ "mov{l}\t{%0, %1|%1, %0}\n\t"
+ "xor{l}\t{%2, %0|%0, %2}\n\t"
+ "push{l}\t%0\n\t"
+ "popf{l|d}\n\t"
+ "pushf{l|d}\n\t"
+ "pop{l}\t%0\n\t"
+ "popf{l|d}\n\t"
: "=&r" (__eax), "=&r" (__ebx)
: "i" (0x00200000));
--
Rask Ingemann Lambertsen
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