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[MIPS 28/30] Remove FPR HImode and QImode handling
- From: Richard Sandiford <rsandifo at nildram dot co dot uk>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 21 Oct 2007 10:25:03 +0100
- Subject: [MIPS 28/30] Remove FPR HImode and QImode handling
- References: <87przc9wms.fsf@firetop.home>
When writing the recent FPR CANNOT_CHANGE_MODE_CLASS patch,
I'd forgotten that we already disallowed QImode and HImode
values in FPRs. The patch below should remove the last bits
of that support.
Richard
gcc/
* config/mips/mips.c (mips_cannot_change_mode_class): Don't check
for modes smaller than 4 bytes.
* config/mips/mips.md (*movhi_internal, *movqi_internal): Remove
FPR alternatives.
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c 2007-10-18 11:07:17.000000000 +0100
+++ gcc/config/mips/mips.c 2007-10-18 11:07:18.000000000 +0100
@@ -8876,14 +8876,8 @@ mips_cannot_change_mode_class (enum mach
- If the FPU has already interpreted a value in one format, we must
not ask it to treat the value as having a different format.
- We therefore only allow changes between 4-byte and smaller integer
- values, all of which have the "W" format as far as the FPU is
- concerned. */
- return (reg_classes_intersect_p (FP_REGS, class)
- && (GET_MODE_CLASS (from) != MODE_INT
- || GET_MODE_CLASS (to) != MODE_INT
- || GET_MODE_SIZE (from) > 4
- || GET_MODE_SIZE (to) > 4));
+ We therefore disallow all mode changes involving FPRs. */
+ return reg_classes_intersect_p (FP_REGS, class);
}
/* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md 2007-10-18 11:07:11.000000000 +0100
+++ gcc/config/mips/mips.md 2007-10-18 11:07:18.000000000 +0100
@@ -3747,8 +3747,8 @@ (define_expand "movhi"
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
- (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
+ (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
@@ -3757,12 +3757,10 @@ (define_insn "*movhi_internal"
li\t%0,%1
lhu\t%0,%1
sh\t%z1,%0
- mfc1\t%0,%1
- mtc1\t%1,%0
mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
+ [(set_attr "type" "move,arith,load,store,mthilo")
(set_attr "mode" "HI")
- (set_attr "length" "4,4,*,*,4,4,4")])
+ (set_attr "length" "4,4,*,*,4")])
(define_insn "*movhi_mips16"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
@@ -3853,8 +3851,8 @@ (define_expand "movqi"
})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
- (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
+ (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
@@ -3863,12 +3861,10 @@ (define_insn "*movqi_internal"
li\t%0,%1
lbu\t%0,%1
sb\t%z1,%0
- mfc1\t%0,%1
- mtc1\t%1,%0
mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
+ [(set_attr "type" "move,arith,load,store,mthilo")
(set_attr "mode" "QI")
- (set_attr "length" "4,4,*,*,4,4,4")])
+ (set_attr "length" "4,4,*,*,4")])
(define_insn "*movqi_mips16"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")