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[PATCH]: Niagara 2 support
- From: David Miller <davem at davemloft dot net>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 18 Oct 2007 21:32:30 -0700 (PDT)
- Subject: [PATCH]: Niagara 2 support
I just added the following patch to mainline which adds
support for Niagara-2 sparc processors. Regstrapped on
sparc-linux-gnu and sparc64-linux-gnu.
/gcc:
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 129471)
+++ doc/invoke.texi (working copy)
@@ -13924,7 +13924,7 @@ for machine type @var{cpu_type}. Suppor
@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
@samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc},
-@samp{ultrasparc3}, and @samp{niagara}.
+@samp{ultrasparc3}, @samp{niagara} and @samp{niagara2}.
Default instruction scheduling parameters are used for values that select
an architecture and not an implementation. These are @samp{v7}, @samp{v8},
@@ -13938,7 +13938,7 @@ implementations.
v8: supersparc, hypersparc
sparclite: f930, f934, sparclite86x
sparclet: tsc701
- v9: ultrasparc, ultrasparc3, niagara
+ v9: ultrasparc, ultrasparc3, niagara, niagara2
@end smallexample
By default (unless configured otherwise), GCC generates code for the V7
@@ -13976,7 +13976,8 @@ optimizes it for the Sun UltraSPARC I/II
@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
@option{-mcpu=niagara}, the compiler additionally optimizes it for
-Sun UltraSPARC T1 chips.
+Sun UltraSPARC T1 chips. With @option{-mcpu=niagara2}, the compiler
+additionally optimizes it for Sun UltraSPARC T2 chips.
@item -mtune=@var{cpu_type}
@opindex mtune
@@ -13989,7 +13990,7 @@ The same values for @option{-mcpu=@var{c
that select a particular cpu implementation. Those are @samp{cypress},
@samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
-@samp{ultrasparc3}, and @samp{niagara}.
+@samp{ultrasparc3}, @samp{niagara}, and @samp{niagara2}.
@item -mv8plus
@itemx -mno-v8plus
Index: ChangeLog
===================================================================
--- ChangeLog (revision 129471)
+++ ChangeLog (working copy)
@@ -1,3 +1,31 @@
+2007-10-18 David S. Miller <davem@davemloft.net>
+
+ Add Niagara-2 support.
+ * doc/invoke.texi: Document -m{cpu,tune}=niagara2.
+ * config.gcc: Add niagara2 to cpu and tune lists for sparc.
+ * config/sparc/sparc.md (sparc_cpu_attr): Add niagara2.
+ (include): Add inclusion of niagara2.md
+ * config/sparc/sparc.c (niagara2_costs): New.
+ (sparc_override_options): Add niagara2 entry to cpu_default[]
+ and cpu_table[]. Set align_functions to 32 on Niagara2. Use
+ niagara2_costs when PROCESSOR_NIAGARA2. Handle Niagara2 for
+ PARAM_SIMULTANEOUS_PREFETCHES and PARAM_L1_CACHE_LINE_SIZE.
+ (sparc_initialize_trampoline): Handle niagara2 like niagara.
+ (sparc64_initialize_trampoline): Likewise.
+ (sparc_use_sched_lookahead): Likewise.
+ (sparc_issue_rate): Likewise.
+ * config/sparc/sol2-bi.h: Handle TARGET_CPU_niagara2 and
+ mcpu=niagara2
+ * config/sparc/sparc.h (TARGET_CPU_niagara2): Define.
+ ({CPP,ASM}_CPU64_DEFAULT_SPEC): Set appropriately for
+ TARGET_CPU_niagara2.
+ (PROCESSOR_NIAGARA2): New.
+ (REGISTER_MOVE_COST): Handle PROCESSOR_NIAGARA2.
+ (BRANCH_COST): Likewise.
+ * config/sparc/linux64.h: Handle TARGET_CPU_niagara2.
+ * config/sparc/sol2.h: Likewise.
+ * config/sparc/niagara2.md: New file.
+
2007-10-18 Richard Sandiford <rsandifo@nildram.co.uk>
* config/mips/mips.c (mips_frame_info): Remove gp_reg_size and
Index: config.gcc
===================================================================
--- config.gcc (revision 129471)
+++ config.gcc (working copy)
@@ -3190,7 +3190,7 @@ case "${target}" in
"" | sparc | sparcv9 | sparc64 | sparc86x \
| v7 | cypress | v8 | supersparc | sparclite | f930 \
| f934 | hypersparc | sparclite86x | sparclet | tsc701 \
- | v9 | ultrasparc | ultrasparc3 | niagara)
+ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2)
# OK
;;
*)
Index: config/sparc/sparc.md
===================================================================
--- config/sparc/sparc.md (revision 129471)
+++ config/sparc/sparc.md (working copy)
@@ -94,7 +94,8 @@ (define_attr "cpu"
v9,
ultrasparc,
ultrasparc3,
- niagara"
+ niagara,
+ niagara2"
(const (symbol_ref "sparc_cpu_attr")))
;; Attribute for the instruction set.
@@ -316,6 +317,7 @@ (define_delay (eq_attr "type" "return")
(include "ultra1_2.md")
(include "ultra3.md")
(include "niagara.md")
+(include "niagara2.md")
;; Operand and operator predicates.
Index: config/sparc/niagara2.md
===================================================================
--- config/sparc/niagara2.md (revision 0)
+++ config/sparc/niagara2.md (revision 0)
@@ -0,0 +1,91 @@
+;; Scheduling description for Niagara-2.
+;; Copyright (C) 2007 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Niagara-2 is a single-issue processor.
+
+(define_automaton "niagara2_0")
+
+(define_cpu_unit "niag2_pipe" "niagara2_0")
+
+(define_insn_reservation "niag2_25cycle" 25
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "flushw"))
+ "niag2_pipe*25")
+
+(define_insn_reservation "niag2_5cycle" 5
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "multi,flushw,iflush,trap"))
+ "niag2_pipe*5")
+
+(define_insn_reservation "niag2_6cycle" 4
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "savew"))
+ "niag2_pipe*4")
+
+/* Most basic operations are single-cycle. */
+(define_insn_reservation "niag2_ialu" 1
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "ialu,shift,compare,cmove"))
+ "niag2_pipe")
+
+(define_insn_reservation "niag2_imul" 5
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "imul"))
+ "niag2_pipe*5")
+
+(define_insn_reservation "niag2_idiv" 31
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "idiv"))
+ "niag2_pipe*31")
+
+(define_insn_reservation "niag2_branch" 5
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
+ "niag2_pipe*5")
+
+(define_insn_reservation "niag2_3cycle_load" 3
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "load,fpload"))
+ "niag2_pipe*3")
+
+(define_insn_reservation "niag2_1cycle_store" 1
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "store,fpstore"))
+ "niag2_pipe")
+
+(define_insn_reservation "niag2_fp" 3
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
+ "niag2_pipe*3")
+
+(define_insn_reservation "niag2_fdivs" 19
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "fpdivs"))
+ "niag2_pipe*19")
+
+(define_insn_reservation "niag2_fdivd" 33
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "fpdivd"))
+ "niag2_pipe*33")
+
+(define_insn_reservation "niag2_vis" 6
+ (and (eq_attr "cpu" "niagara2")
+ (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+ "niag2_pipe*6")
Index: config/sparc/sparc.c
===================================================================
--- config/sparc/sparc.c (revision 129471)
+++ config/sparc/sparc.c (working copy)
@@ -222,6 +222,30 @@ struct processor_costs niagara_costs = {
0, /* shift penalty */
};
+static const
+struct processor_costs niagara2_costs = {
+ COSTS_N_INSNS (3), /* int load */
+ COSTS_N_INSNS (3), /* int signed load */
+ COSTS_N_INSNS (3), /* int zeroed load */
+ COSTS_N_INSNS (3), /* float load */
+ COSTS_N_INSNS (6), /* fmov, fneg, fabs */
+ COSTS_N_INSNS (6), /* fadd, fsub */
+ COSTS_N_INSNS (6), /* fcmp */
+ COSTS_N_INSNS (6), /* fmov, fmovr */
+ COSTS_N_INSNS (6), /* fmul */
+ COSTS_N_INSNS (19), /* fdivs */
+ COSTS_N_INSNS (33), /* fdivd */
+ COSTS_N_INSNS (19), /* fsqrts */
+ COSTS_N_INSNS (33), /* fsqrtd */
+ COSTS_N_INSNS (5), /* imul */
+ COSTS_N_INSNS (5), /* imulX */
+ 0, /* imul bit factor */
+ COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
+ COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
+ COSTS_N_INSNS (1), /* movcc/movr */
+ 0, /* shift penalty */
+};
+
const struct processor_costs *sparc_costs = &cypress_costs;
#ifdef HAVE_AS_RELAX_OPTION
@@ -623,6 +647,7 @@ sparc_override_options (void)
{ TARGET_CPU_ultrasparc, "ultrasparc" },
{ TARGET_CPU_ultrasparc3, "ultrasparc3" },
{ TARGET_CPU_niagara, "niagara" },
+ { TARGET_CPU_niagara2, "niagara2" },
{ 0, 0 }
};
const struct cpu_default *def;
@@ -660,6 +685,7 @@ sparc_override_options (void)
{ "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
/* UltraSPARC T1 */
{ "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
+ { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
{ 0, 0, 0, 0 }
};
const struct cpu_table *cpu;
@@ -770,7 +796,8 @@ sparc_override_options (void)
if (align_functions == 0
&& (sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3
- || sparc_cpu == PROCESSOR_NIAGARA))
+ || sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2))
align_functions = 32;
/* Validate PCC_STRUCT_RETURN. */
@@ -822,6 +849,9 @@ sparc_override_options (void)
case PROCESSOR_NIAGARA:
sparc_costs = &niagara_costs;
break;
+ case PROCESSOR_NIAGARA2:
+ sparc_costs = &niagara2_costs;
+ break;
};
#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
@@ -832,7 +862,8 @@ sparc_override_options (void)
if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
set_param_value ("simultaneous-prefetches",
((sparc_cpu == PROCESSOR_ULTRASPARC
- || sparc_cpu == PROCESSOR_NIAGARA)
+ || sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2)
? 2
: (sparc_cpu == PROCESSOR_ULTRASPARC3
? 8 : 3)));
@@ -840,7 +871,8 @@ sparc_override_options (void)
set_param_value ("l1-cache-line-size",
((sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3
- || sparc_cpu == PROCESSOR_NIAGARA)
+ || sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2)
? 64 : 32));
}
@@ -7236,7 +7268,8 @@ sparc_initialize_trampoline (rtx tramp,
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
if (sparc_cpu != PROCESSOR_ULTRASPARC
&& sparc_cpu != PROCESSOR_ULTRASPARC3
- && sparc_cpu != PROCESSOR_NIAGARA)
+ && sparc_cpu != PROCESSOR_NIAGARA
+ && sparc_cpu != PROCESSOR_NIAGARA2)
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
plus_constant (tramp, 8)))));
@@ -7279,7 +7312,8 @@ sparc64_initialize_trampoline (rtx tramp
if (sparc_cpu != PROCESSOR_ULTRASPARC
&& sparc_cpu != PROCESSOR_ULTRASPARC3
- && sparc_cpu != PROCESSOR_NIAGARA)
+ && sparc_cpu != PROCESSOR_NIAGARA
+ && sparc_cpu != PROCESSOR_NIAGARA2)
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
/* Call __enable_execute_stack after writing onto the stack to make sure
@@ -7459,7 +7493,8 @@ sparc_sched_init (FILE *dump ATTRIBUTE_U
static int
sparc_use_sched_lookahead (void)
{
- if (sparc_cpu == PROCESSOR_NIAGARA)
+ if (sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2)
return 0;
if (sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3)
@@ -7477,6 +7512,7 @@ sparc_issue_rate (void)
switch (sparc_cpu)
{
case PROCESSOR_NIAGARA:
+ case PROCESSOR_NIAGARA2:
default:
return 1;
case PROCESSOR_V9:
Index: config/sparc/sol2-bi.h
===================================================================
--- config/sparc/sol2-bi.h (revision 129471)
+++ config/sparc/sol2-bi.h (working copy)
@@ -48,6 +48,15 @@
#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#endif
+
#if DEFAULT_ARCH32_P
#define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
#define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
@@ -66,7 +75,7 @@
%{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
%{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
%{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
@@ -76,7 +85,8 @@
%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
%{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
%{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
-%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}} \
+%{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
+%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}}} \
%{!mcpu*:%(asm_cpu_default)} \
"
Index: config/sparc/sparc.h
===================================================================
--- config/sparc/sparc.h (revision 129471)
+++ config/sparc/sparc.h (working copy)
@@ -207,7 +207,8 @@ extern enum cmodel sparc_cmodel;
which requires the following macro to be true if enabled. Prior to V9,
there are no instructions to even talk about memory synchronization.
Note that the UltraSPARC III processors don't implement RMO, unlike the
- UltraSPARC II processors. Niagara does not implement RMO either.
+ UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
+ either.
Default to false; for example, Solaris never enables RMO, only ever uses
total memory ordering (TMO). */
@@ -240,11 +241,13 @@ extern enum cmodel sparc_cmodel;
#define TARGET_CPU_ultrasparc 8
#define TARGET_CPU_ultrasparc3 9
#define TARGET_CPU_niagara 10
+#define TARGET_CPU_niagara2 11
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
#define CPP_CPU32_DEFAULT_SPEC ""
#define ASM_CPU32_DEFAULT_SPEC ""
@@ -269,6 +272,10 @@ extern enum cmodel sparc_cmodel;
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
#else
@@ -360,6 +367,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
%{mcpu=niagara:-D__sparc_v9__} \
+%{mcpu=niagara2:-D__sparc_v9__} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
#define CPP_ARCH32_SPEC ""
@@ -410,6 +418,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
%{mcpu=niagara:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
"
@@ -534,7 +543,8 @@ enum processor_type {
PROCESSOR_V9,
PROCESSOR_ULTRASPARC,
PROCESSOR_ULTRASPARC3,
- PROCESSOR_NIAGARA
+ PROCESSOR_NIAGARA,
+ PROCESSOR_NIAGARA2
};
/* This is set from -m{cpu,tune}=xxx. */
@@ -2155,7 +2165,8 @@ do {
|| (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
? ((sparc_cpu == PROCESSOR_ULTRASPARC \
|| sparc_cpu == PROCESSOR_ULTRASPARC3 \
- || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
+ || sparc_cpu == PROCESSOR_NIAGARA \
+ || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
/* Provide the cost of a branch. For pre-v9 processors we use
a value of 3 to take into account the potential annulling of
@@ -2168,7 +2179,10 @@ do {
mispredicted branch.
On Niagara, normal branches insert 3 bubbles into the pipe
- and annulled branches insert 4 bubbles. */
+ and annulled branches insert 4 bubbles.
+
+ On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
+ branch costs 6 cycles. */
#define BRANCH_COST \
((sparc_cpu == PROCESSOR_V9 \
@@ -2178,7 +2192,9 @@ do {
? 9 \
: (sparc_cpu == PROCESSOR_NIAGARA \
? 4 \
- : 3)))
+ : (sparc_cpu == PROCESSOR_NIAGARA2 \
+ ? 5 \
+ : 3))))
/* Control the assembler format that we output. */
Index: config/sparc/linux64.h
===================================================================
--- config/sparc/linux64.h (revision 129471)
+++ config/sparc/linux64.h (working copy)
@@ -43,7 +43,8 @@ along with GCC; see the file COPYING3.
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
/* A 64 bit v9 compiler with stack-bias,
in a Medium/Low code model environment. */
Index: config/sparc/sol2.h
===================================================================
--- config/sparc/sol2.h (revision 129471)
+++ config/sparc/sol2.h (working copy)
@@ -45,12 +45,18 @@ along with GCC; see the file COPYING3.
#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#undef ASM_CPU_DEFAULT_SPEC
+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
+#endif
+
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "\
%{mcpu=v9:-xarch=v8plus} \
%{mcpu=ultrasparc:-xarch=v8plusa} \
%{mcpu=ultrasparc3:-xarch=v8plusb} \
%{mcpu=niagara:-xarch=v8plusb} \
+%{mcpu=niagara2:-xarch=v8plusb} \
%{!mcpu*:%(asm_cpu_default)} \
"