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Re: SSE5 patches round 3
Hello!
Just a quick suggestion:
+ ;; We don't have a straight 32-bit parallel multiply on SSE5, so fake it with a
+ ;; multiply/add.
+ (define_insn_and_split "*sse5_mulv4si3"
+ [(set (match_operand:V4SI 0 "register_operand" "=&x")
+ (mult:V4SI (match_operand:V4SI 1 "register_operand" "%x")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
+ "TARGET_SSE5"
+ "#"
+ "TARGET_SSE5
+ && (reload_completed
+ || (!reg_mentioned_p (operands[0], operands[1])
+ && !reg_mentioned_p (operands[0], operands[2])))"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 0)
+ (plus:V4SI (mult:V4SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))]
+ {
+ operands[3] = CONST0_RTX (V4SImode);
+ }
+ [(set_attr "type" "ssemuladd")
+ (set_attr "mode" "TI")])
+
This splitter does not need to be post-reload splitter. If you split
this insn before register allocation, then allocator will solve all
register conflicts for you:
+ (define_insn_and_split "*sse5_mulv4si3"
+ [(set (match_operand:V4SI 0 "register_operand" "")
+ (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
+ (match_operand:V4SI 2 "nonimmediate_operand" "")))]
+ "TARGET_SSE5
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (match_dup 3))
+ (set (match_dup 0)
+ (plus:V4SI (mult:V4SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))]
+ {
+ operands[3] = CONST0_RTX (V4SImode);
+ }
+ [(set_attr "type" "ssemuladd")
+ (set_attr "mode" "TI")])
Uros.