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Re: RFC: [PATCH] MIPS: Implement built-in atomic memory operations.
On Mon, 13 Aug 2007, David Daney wrote:
> > It is implementation-specific how much address space is checked by the LL/SC
> > logic for bus activity, so if you have another load (or store) between an LL
> > and an SC chances are the SC will never succeed.
> >
>
> Right. It is clear that although with my original patch correct code is
> generated for simple test cases, in general there is the possibility of
> generating bad code.
Yeah, it would be nice to have an ability to mark a block of code as
prohibited from data memory accesses, but at the moment I do not even have
an idea of how it might look like. Such a feature would permit (almost)
arbitrarily complicated atomic RMW operations as LL/SC is probably as
flexible as you can get.
Maciej