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Re: PATCH: Add MIPS 4ksc and 4ksd processors
- From: Thiemo Seufer <ths at networkno dot de>
- To: Sandra Loosemore <sandra at codesourcery dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, David Ung <davidu at mips dot com>, Nigel Stephens <nigel at mips dot com>, Guy Morrogh <guym at mips dot com>, richard at codesourcery dot com
- Date: Wed, 4 Jul 2007 20:16:26 +0100
- Subject: Re: PATCH: Add MIPS 4ksc and 4ksd processors
- References: <468BCC67.8040608@codesourcery.com> <873b04dkr4.fsf@firetop.home>
Richard Sandiford wrote:
> Sandra Loosemore <sandra@codesourcery.com> writes:
> > 2007-07-04 Sandra Loosemore <sandra@codesourcery.com>
> > David Ung <davidu@mips.com>
> >
> > gcc/
> > * config/mips/mips.c (mips_cpu_info): Add 4ksc and 4ksd processors.
> > * doc/invoke.texi: (MIPS Options): Document them.
>
> OK, thanks.
>
> I take David's point that it would be a good idea to enable -msmartmips
> by default, but I think that's a separate change. We don't enable other
> processors' ASEs by default either, and we don't have any specific
> infrastructure to do so. When we implement it, we should implement
> it consistently.
JFTR, the assembler does that already.
Thiemo