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[PATCH] S/390: DFP support 3/4: Rename mode macro FPR to BFP
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Ulrich dot Weigand at de dot ibm dot com
- Date: Fri, 16 Mar 2007 20:02:24 +0100
- Subject: [PATCH] S/390: DFP support 3/4: Rename mode macro FPR to BFP
Hi,
the third patch is a non-functional change I've separated to allow for
easier reviewing. The patch renames the FPR mode macro to BFP all over
the s390.md file.
Bootstrapped with the other patches on s390 and s390x.
OK for mainline?
Bye,
-Andreas-
2007-03-16 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md: Only non-functional changes. Renamed
FPR mode macro to BFP all over the file.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2007-03-16 09:43:37.000000000 +0100
--- gcc/config/s390/s390.md 2007-03-16 09:43:50.000000000 +0100
***************
*** 214,220 ****
;; This mode macro allows floating point patterns to be generated from the
;; same template.
! (define_mode_macro FPR [TF DF SF])
(define_mode_macro DSF [DF SF])
;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
--- 214,220 ----
;; This mode macro allows floating point patterns to be generated from the
;; same template.
! (define_mode_macro BFP [TF DF SF])
(define_mode_macro DSF [DF SF])
;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
***************
*** 256,275 ****
(plus "add") (minus "sub") (mult "nand")])
! ;; In FPR templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
;; "ltdbr" in DFmode, and "ltebr" in SFmode.
(define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
! ;; In FPR templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
;; "mdbr" in DFmode, and "meebr" in SFmode.
(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
! ;; In FPR templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
;; Likewise for "<RXe>".
(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
! ;; In FPR templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
;; This is used to disable the memory alternative in TFmode patterns.
(define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
--- 256,275 ----
(plus "add") (minus "sub") (mult "nand")])
! ;; In BFP templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
;; "ltdbr" in DFmode, and "ltebr" in SFmode.
(define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
! ;; In BFP templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
;; "mdbr" in DFmode, and "meebr" in SFmode.
(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
! ;; In BFP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
;; Likewise for "<RXe>".
(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
! ;; In BFP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
;; This is used to disable the memory alternative in TFmode patterns.
(define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
***************
*** 362,369 ****
(define_expand "cmp<mode>"
[(set (reg:CC CC_REGNUM)
! (compare:CC (match_operand:FPR 0 "register_operand" "")
! (match_operand:FPR 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
{
s390_compare_op0 = operands[0];
--- 362,369 ----
(define_expand "cmp<mode>"
[(set (reg:CC CC_REGNUM)
! (compare:CC (match_operand:BFP 0 "register_operand" "")
! (match_operand:BFP 1 "general_operand" "")))]
"TARGET_HARD_FLOAT"
{
s390_compare_op0 = operands[0];
***************
*** 753,760 ****
; ltxbr, ltdbr, ltebr
(define_insn "*cmp<mode>_ccs_0"
[(set (reg CC_REGNUM)
! (compare (match_operand:FPR 0 "register_operand" "f")
! (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lt<xde>br\t%0,%0"
[(set_attr "op_type" "RRE")
--- 753,760 ----
; ltxbr, ltdbr, ltebr
(define_insn "*cmp<mode>_ccs_0"
[(set (reg CC_REGNUM)
! (compare (match_operand:BFP 0 "register_operand" "f")
! (match_operand:BFP 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lt<xde>br\t%0,%0"
[(set_attr "op_type" "RRE")
***************
*** 763,770 ****
; ltxr, ltdr, lter
(define_insn "*cmp<mode>_ccs_0_ibm"
[(set (reg CC_REGNUM)
! (compare (match_operand:FPR 0 "register_operand" "f")
! (match_operand:FPR 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lt<xde>r\t%0,%0"
[(set_attr "op_type" "<RRe>")
--- 763,770 ----
; ltxr, ltdr, lter
(define_insn "*cmp<mode>_ccs_0_ibm"
[(set (reg CC_REGNUM)
! (compare (match_operand:BFP 0 "register_operand" "f")
! (match_operand:BFP 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lt<xde>r\t%0,%0"
[(set_attr "op_type" "<RRe>")
***************
*** 773,780 ****
; cxbr, cdbr, cebr, cxb, cdb, ceb
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
! (compare (match_operand:FPR 0 "register_operand" "f,f")
! (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
c<xde>br\t%0,%1
--- 773,780 ----
; cxbr, cdbr, cebr, cxb, cdb, ceb
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
! (compare (match_operand:BFP 0 "register_operand" "f,f")
! (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
c<xde>br\t%0,%1
***************
*** 785,792 ****
; cxr, cdr, cer, cx, cd, ce
(define_insn "*cmp<mode>_ccs_ibm"
[(set (reg CC_REGNUM)
! (compare (match_operand:FPR 0 "register_operand" "f,f")
! (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
c<xde>r\t%0,%1
--- 785,792 ----
; cxr, cdr, cer, cx, cd, ce
(define_insn "*cmp<mode>_ccs_ibm"
[(set (reg CC_REGNUM)
! (compare (match_operand:BFP 0 "register_operand" "f,f")
! (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
c<xde>r\t%0,%1
***************
*** 1554,1560 ****
operands[1] = replace_equiv_address (operands[1], addr);
})
! ; TFmode in FPRs splitters
(define_split
[(set (match_operand:TF 0 "register_operand" "")
--- 1554,1560 ----
operands[1] = replace_equiv_address (operands[1], addr);
})
! ; TFmode in BFPs splitters
(define_split
[(set (match_operand:TF 0 "register_operand" "")
***************
*** 3148,3178 ****
; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
;
! (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "")
! (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
! rtx temp = gen_reg_rtx (<FPR:MODE>mode);
REAL_VALUE_TYPE cmp, sub;
! operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
! emit_insn (gen_cmp<FPR:mode> (operands[1],
! CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
emit_jump_insn (gen_blt (label1));
! emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
! CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
! emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
GEN_INT(7)));
emit_jump (label2);
emit_label (label1);
! emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
operands[1], GEN_INT(5)));
emit_label (label2);
DONE;
--- 3148,3178 ----
; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
;
! (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "")
! (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
{
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
! rtx temp = gen_reg_rtx (<BFP:MODE>mode);
REAL_VALUE_TYPE cmp, sub;
! operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
! emit_insn (gen_cmp<BFP:mode> (operands[1],
! CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
emit_jump_insn (gen_blt (label1));
! emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
! CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
! emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0], temp,
GEN_INT(7)));
emit_jump (label2);
emit_label (label1);
! emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0],
operands[1], GEN_INT(5)));
emit_label (label2);
DONE;
***************
*** 3190,3202 ****
})
; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
! (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
! "c<GPR:gf><FPR:xde>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
--- 3190,3202 ----
})
; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
! (define_insn "fix_trunc<BFP:mode><GPR:mode>2_ieee"
[(set (match_operand:GPR 0 "register_operand" "=d")
! (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
! "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
***************
*** 3290,3297 ****
; cxgbr, cdgbr, cegbr
(define_insn "floatdi<mode>2"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (float:FPR (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"c<xde>gbr\t%0,%1"
[(set_attr "op_type" "RRE")
--- 3290,3297 ----
; cxgbr, cdgbr, cegbr
(define_insn "floatdi<mode>2"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (float:BFP (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"c<xde>gbr\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 3299,3306 ****
; cxfbr, cdfbr, cefbr
(define_insn "floatsi<mode>2_ieee"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (float:FPR (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"c<xde>fbr\t%0,%1"
[(set_attr "op_type" "RRE")
--- 3299,3306 ----
; cxfbr, cdfbr, cefbr
(define_insn "floatsi<mode>2_ieee"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (float:BFP (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"c<xde>fbr\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 3883,3900 ****
(define_expand "add<mode>3"
[(parallel
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3883,3900 ----
(define_expand "add<mode>3"
[(parallel
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3906,3916 ****
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
! (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>"))
! (match_operand:FPR 3 "const0_operand" "")))
! (set (match_operand:FPR 0 "register_operand" "=f,f")
! (plus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
a<xde>br\t%0,%2
--- 3906,3916 ----
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
! (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>"))
! (match_operand:BFP 3 "const0_operand" "")))
! (set (match_operand:BFP 0 "register_operand" "=f,f")
! (plus:BFP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
a<xde>br\t%0,%2
***************
*** 3921,3930 ****
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
! (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>"))
! (match_operand:FPR 3 "const0_operand" "")))
! (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
a<xde>br\t%0,%2
--- 3921,3930 ----
; axbr, adbr, aebr, axb, adb, aeb
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
! (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>"))
! (match_operand:BFP 3 "const0_operand" "")))
! (clobber (match_scratch:BFP 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
a<xde>br\t%0,%2
***************
*** 3934,3942 ****
; axr, adr, aer, ax, ad, ae
(define_insn "*add<mode>3_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3934,3942 ----
; axr, adr, aer, ax, ad, ae
(define_insn "*add<mode>3_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 4226,4243 ****
(define_expand "sub<mode>3"
[(parallel
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,R")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 4226,4243 ----
(define_expand "sub<mode>3"
[(parallel
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,R")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 4249,4259 ****
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
! (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>"))
! (match_operand:FPR 3 "const0_operand" "")))
! (set (match_operand:FPR 0 "register_operand" "=f,f")
! (minus:FPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
s<xde>br\t%0,%2
--- 4249,4259 ----
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
! (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>"))
! (match_operand:BFP 3 "const0_operand" "")))
! (set (match_operand:BFP 0 "register_operand" "=f,f")
! (minus:BFP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
s<xde>br\t%0,%2
***************
*** 4264,4273 ****
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
! (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>"))
! (match_operand:FPR 3 "const0_operand" "")))
! (clobber (match_scratch:FPR 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
s<xde>br\t%0,%2
--- 4264,4273 ----
; sxbr, sdbr, sebr, sxb, sdb, seb
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
! (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>"))
! (match_operand:BFP 3 "const0_operand" "")))
! (clobber (match_scratch:BFP 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
s<xde>br\t%0,%2
***************
*** 4277,4285 ****
; sxr, sdr, ser, sx, sd, se
(define_insn "*sub<mode>3_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 4277,4285 ----
; sxr, sdr, ser, sx, sd, se
(define_insn "*sub<mode>3_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 4535,4551 ****
;
(define_expand "mul<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
"")
; mxbr mdbr, meebr, mxb, mxb, meeb
(define_insn "*mul<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
m<xdee>br\t%0,%2
--- 4535,4551 ----
;
(define_expand "mul<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
"")
; mxbr mdbr, meebr, mxb, mxb, meeb
(define_insn "*mul<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
m<xdee>br\t%0,%2
***************
*** 4555,4563 ****
; mxr, mdr, mer, mx, md, me
(define_insn "*mul<mode>3_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
m<xde>r\t%0,%2
--- 4555,4563 ----
; mxr, mdr, mer, mx, md, me
(define_insn "*mul<mode>3_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
m<xde>r\t%0,%2
***************
*** 5014,5030 ****
;
(define_expand "div<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
"")
; dxbr, ddbr, debr, dxb, ddb, deb
(define_insn "*div<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
d<xde>br\t%0,%2
--- 5014,5030 ----
;
(define_expand "div<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT"
"")
; dxbr, ddbr, debr, dxb, ddb, deb
(define_insn "*div<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
d<xde>br\t%0,%2
***************
*** 5034,5042 ****
; dxr, ddr, der, dx, dd, de
(define_insn "*div<mode>3_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
! (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
d<xde>r\t%0,%2
--- 5034,5042 ----
; dxr, ddr, der, dx, dd, de
(define_insn "*div<mode>3_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
! (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
d<xde>r\t%0,%2
***************
*** 6014,6021 ****
(define_expand "neg<mode>2"
[(parallel
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
--- 6014,6021 ----
(define_expand "neg<mode>2"
[(parallel
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 6023,6032 ****
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
! (match_operand:FPR 2 "const0_operand" "")))
! (set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6023,6032 ----
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
! (match_operand:BFP 2 "const0_operand" "")))
! (set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6035,6043 ****
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
! (match_operand:FPR 2 "const0_operand" "")))
! (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6035,6043 ----
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
! (match_operand:BFP 2 "const0_operand" "")))
! (clobber (match_scratch:BFP 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6045,6052 ****
; lcdfr
(define_insn "*neg<mode>2_nocc"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (match_operand:FPR 1 "register_operand" "<fT0>")))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lcdfr\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6045,6052 ----
; lcdfr
(define_insn "*neg<mode>2_nocc"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lcdfr\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6054,6061 ****
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
--- 6054,6061 ----
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lc<xde>br\t%0,%1"
***************
*** 6064,6071 ****
; lcxr, lcdr, lcer
(define_insn "*neg<mode>2_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lc<xde>r\t%0,%1"
--- 6064,6071 ----
; lcxr, lcdr, lcer
(define_insn "*neg<mode>2_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lc<xde>r\t%0,%1"
***************
*** 6137,6144 ****
(define_expand "abs<mode>2"
[(parallel
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
--- 6137,6144 ----
(define_expand "abs<mode>2"
[(parallel
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 6146,6155 ****
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
! (match_operand:FPR 2 "const0_operand" "")))
! (set (match_operand:FPR 0 "register_operand" "=f")
! (abs:FPR (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6146,6155 ----
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
! (match_operand:BFP 2 "const0_operand" "")))
! (set (match_operand:BFP 0 "register_operand" "=f")
! (abs:BFP (match_dup 1)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6158,6166 ****
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
! (match_operand:FPR 2 "const0_operand" "")))
! (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6158,6166 ----
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
! (match_operand:BFP 2 "const0_operand" "")))
! (clobber (match_scratch:BFP 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6168,6175 ****
; lpdfr
(define_insn "*abs<mode>2_nocc"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (abs:FPR (match_operand:FPR 1 "register_operand" "<fT0>")))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lpdfr\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6168,6175 ----
; lpdfr
(define_insn "*abs<mode>2_nocc"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lpdfr\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6177,6184 ****
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
--- 6177,6184 ----
; lpxbr, lpdbr, lpebr
(define_insn "*abs<mode>2"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lp<xde>br\t%0,%1"
***************
*** 6187,6194 ****
; lpxr, lpdr, lper
(define_insn "*abs<mode>2_ibm"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lp<xde>r\t%0,%1"
--- 6187,6194 ----
; lpxr, lpdr, lper
(define_insn "*abs<mode>2_ibm"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lp<xde>r\t%0,%1"
***************
*** 6261,6270 ****
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
! (match_operand:FPR 2 "const0_operand" "")))
! (set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (abs:FPR (match_dup 1))))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6261,6270 ----
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cc"
[(set (reg CC_REGNUM)
! (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
! (match_operand:BFP 2 "const0_operand" "")))
! (set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (abs:BFP (match_dup 1))))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6273,6281 ****
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
! (match_operand:FPR 2 "const0_operand" "")))
! (clobber (match_scratch:FPR 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6273,6281 ----
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2_cconly"
[(set (reg CC_REGNUM)
! (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
! (match_operand:BFP 2 "const0_operand" "")))
! (clobber (match_scratch:BFP 0 "=f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6283,6290 ****
; lndfr
(define_insn "*negabs<mode>2_nocc"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "<fT0>"))))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lndfr\t%0,%1"
[(set_attr "op_type" "RRE")
--- 6283,6290 ----
; lndfr
(define_insn "*negabs<mode>2_nocc"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"lndfr\t%0,%1"
[(set_attr "op_type" "RRE")
***************
*** 6292,6299 ****
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
--- 6292,6299 ----
; lnxbr, lndbr, lnebr
(define_insn "*negabs<mode>2"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ln<xde>br\t%0,%1"
***************
*** 6306,6314 ****
; cpsdr
(define_insn "copysign<mode>3"
! [(set (match_operand:FPR 0 "register_operand" "=f")
! (unspec:FPR [(match_operand:FPR 1 "register_operand" "<fT0>")
! (match_operand:FPR 2 "register_operand" "f")]
UNSPEC_COPYSIGN))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"cpsdr\t%0,%2,%1"
--- 6306,6314 ----
; cpsdr
(define_insn "copysign<mode>3"
! [(set (match_operand:BFP 0 "register_operand" "=f")
! (unspec:BFP [(match_operand:BFP 1 "register_operand" "<fT0>")
! (match_operand:BFP 2 "register_operand" "f")]
UNSPEC_COPYSIGN))]
"TARGET_HARD_FLOAT && TARGET_DFP"
"cpsdr\t%0,%2,%1"
***************
*** 6325,6332 ****
; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
(define_insn "sqrt<mode>2"
! [(set (match_operand:FPR 0 "register_operand" "=f,f")
! (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sq<xde>br\t%0,%1
--- 6325,6332 ----
; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
(define_insn "sqrt<mode>2"
! [(set (match_operand:BFP 0 "register_operand" "=f,f")
! (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sq<xde>br\t%0,%1