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PATCH: typos in invoke.texi (was: [PING] typo patch)
:ADDPATCH documentation:
gcc/ChangeLog:
2007-01-30 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* doc/invoke.texi (C++ Dialect Options, Debugging Options)
(Optimize Options, HPPA Options, i386 and x86-64 Options)
(IA-64 Options, RS/6000 and PowerPC Options): Fix spacing after
abbreviations. Fix some typos.
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 121314)
+++ gcc/doc/invoke.texi (working copy)
@@ -1609,7 +1609,7 @@
of the language, you can save some space by using this flag. Note that
exception handling uses the same information, but it will generate it as
needed. The @samp{dynamic_cast} operator can still be used for casts that
-do not require runtime type information, i.e. casts to @code{void *} or to
+do not require runtime type information, i.e., casts to @code{void *} or to
unambiguous base classes.
@item -fstats
@@ -4385,7 +4385,7 @@
If @var{n}=1 the vectorizer reports each loop that got vectorized,
and the total number of loops that got vectorized.
If @var{n}=2 the vectorizer also reports non-vectorized loops that passed
-the first analysis phase (vect_analyze_loop_form) - i.e. countable,
+the first analysis phase (vect_analyze_loop_form) - i.e., countable,
inner-most, single-bb, single-entry/exit loops. This is the same verbosity
level that @option{-fdump-tree-vect-stats} uses.
Higher verbosity levels mean either more information dumped for each
@@ -4394,7 +4394,7 @@
If @var{n}=4, data-references related information (e.g. memory dependences,
memory access-patterns) is added to the reports.
If @var{n}=5, the vectorizer reports also non-vectorized inner-most loops
-that did not pass the first analysis phase (i.e. may not be countable, or
+that did not pass the first analysis phase (i.e., may not be countable, or
may have complicated control-flow).
If @var{n}=6, the vectorizer reports also non-vectorized nested loops.
For @var{n}=7, all the information the vectorizer generates during its
@@ -6137,7 +6137,7 @@
For small units this might be too tight (consider unit consisting of function A
that is inline and B that just calls A three time. If B is small relative to
A, the growth of unit is 300\% and yet such inlining is very sane. For very
-large units consisting of small inlininable functions however the overall unit
+large units consisting of small inlineable functions however the overall unit
growth limit is needed to avoid exponential explosion of code size. Thus for
smaller units, the size is increased to @option{--param large-unit-insns}
before applying @option{--param inline-unit-growth}. The default is 10000
@@ -6436,7 +6436,7 @@
@item integer-share-limit
Small integer constants can use a shared data structure, reducing the
compiler's memory usage and increasing its speed. This sets the maximum
-value of a shared integer constant's. The default value is 256.
+value of a shared integer constant. The default value is 256.
@item min-virtual-mappings
Specifies the minimum number of virtual mappings in the incremental
@@ -6451,7 +6451,7 @@
ratio is 3.
@item ssp-buffer-size
-The minimum size of buffers (i.e. arrays) that will receive stack smashing
+The minimum size of buffers (i.e., arrays) that will receive stack smashing
protection when @option{-fstack-protection} is used.
@item max-jump-thread-duplication-stmts
@@ -9307,7 +9307,7 @@
@option{--with-ld} configure option, GCC's program search path, and
finally by the user's @env{PATH}. The linker used by GCC can be printed
using @samp{which `gcc -print-prog-name=ld`}. This option is only available
-on the 64 bit HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
+on the 64 bit HP-UX GCC, i.e., configured with @samp{hppa*64*-*-hpux*}.
@item -mhp-ld
@opindex hp-ld
@@ -9320,7 +9320,7 @@
configure option, GCC's program search path, and finally by the user's
@env{PATH}. The linker used by GCC can be printed using @samp{which
`gcc -print-prog-name=ld`}. This option is only available on the 64 bit
-HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
+HP-UX GCC, i.e., configured with @samp{hppa*64*-*-hpux*}.
@item -mlong-calls
@opindex mno-long-calls
@@ -9477,24 +9477,24 @@
@item k6
AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3
-Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
+Improved versions of AMD K6 CPU with MMX and 3dNOW!@: instruction set support.
@item athlon, athlon-tbird
-AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
+AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and SSE prefetch instructions
support.
@item athlon-4, athlon-xp, athlon-mp
-Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
+Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and full SSE
instruction set support.
@item k8, opteron, athlon64, athlon-fx
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
-MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
+MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW!@: and 64-bit instruction set extensions.)
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
@item winchip2
-IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
+IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!@:
instruction set support.
@item c3
-Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
+Via C3 CPU with MMX and 3dNOW!@: instruction set support. (No scheduling is
implemented for this chip.)
@item c3-2
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
@@ -9790,7 +9790,7 @@
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3 or 3DNow! extended instruction sets.
+SSE, SSE2, SSE3, SSSE3 or 3DNow!@: extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
disabled by these switches.
@@ -10097,7 +10097,7 @@
@opindex -mno-sched-control-spec
@opindex -msched-control-spec
(Dis/En)able control speculative scheduling. This feature is
-available only during region scheduling (i.e. before reload).
+available only during region scheduling (i.e., before reload).
This will result in generation of the ld.s instructions and
the corresponding check instructions chk.s .
The default is 'disable'.
@@ -12228,7 +12228,7 @@
@opindex msim
On embedded PowerPC systems, assume that the startup module is called
@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
-@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
+@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}
configurations.
@item -mmvme