Re: [RTL, ColdFire 24/63] Add support for a MODE_INDEX_REG_CLASS macro

[Richard Sandiford <richard at codesourcery dot com>]

Jeffrey Law <law@redhat.com> writes:
> On Wed, 2007-01-10 at 11:23 +0000, Richard Sandiford wrote:
>> At the moment, gcc expects there to be a single INDEX_REG_CLASS that
>> applies to all MEM modes.  This is not true when using a ColdFire FPU,
>> as index registers are not allowed for floating-point modes.  The port
>> tries to hack around this by using "<Q>U" instead of "m" in the movsf
>> constraints, but that's only a half solution.  If reload has to reload
>> an indexed MEM (rather than the MEM's address), it will expect that
>> instruction to match.
>> 
>> The fix is to allow the class of index register to vary depending on
>> the mode of the addressed value, as the base register class already can.
>> 
>> This patch does the target-independent bit.  It adds new target macros
>> called MODE_INDEX_REG_CLASS and REGNO_MODE_OK_FOR_INDEX_P, to accompany
>> the existing MODE_BASE_REG_CLASS and REGNO_MODE_OK_FOR_BASE_P.  It also
>> defines index equivalents of the addresses.h base functions.  This is
>> all a direct image of the base register code (including the wording
>> of comments and documentation).  I think the two should be consistent.
>> The patch then adjusts all code to use thse new addresses.h functions.
>> 
>> Bootstrapped & regression-tested on x86_64-linux-gnu.
> Umm, I'm not sure this is safe, though maybe I'm misunderstanding
> something.
>
> The fundamental problem as I see it is that there are addressing
> modes which are sometimes valid and sometimes not valid.  In this
> particular case whether or not the addressing mode is valid is a
> function of whether or not the load/store is an FPU load/store.

Right, that describes the ISA restrictions.  But this patch isn't
really about the ISA restrictions per se.  The m68k port makes a pragmatic
decision to forbid indexed addressing modes for _all_ SFmode and DFmode
MEMs if TARGET_COLDFIRE_FPU, on the basis that the vast majority of
memory accesses will be in FPU instructions.  We then expose the
necessary addressing code to the pre-reload optimisers and register
allocators, rather than leaving reload to find scratch address registers
from somewhere.  Although I didn't make that decision (it's what current
mainline does), I can well imagine that it leads to better code.

In other words, this is entirely an internal gcc thing.  The current
definition of INDEX_REG_CLASS tricks reload into thinking that indexed
addressing modes are acceptable SFmode and DFmode memory_operands,
which they aren't.  It will then use such memories in copy-in and
copy-out reload instructions.

Richard