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[ColdFire 41/63] Add support for the ff1 instruction
This patch adds support for the ISA A+ and ISA C ff1 instruction.
Richard
gcc/
200x-xx-xx Sandra Loosemore <sandra@codesourcery.com>
* longlong.h (count_leading_zeros, COUNT_LEADING_ZEROS_0): Add
ColdFire alternatives.
* config/m68k/m68k.h (CLZ_DEFINED_VALUE_AT_ZERO): New macro.
* config/m68k/m68k.md (clzsi2): Define for ColdFire
architectures that support ff1 instruction.
Index: gcc/longlong.h
===================================================================
--- gcc/longlong.h 2007-01-09 13:18:11.000000000 +0000
+++ gcc/longlong.h 2007-01-09 15:02:18.000000000 +0000
@@ -521,6 +521,11 @@ #define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
: "=d" ((USItype) (count)) \
: "od" ((USItype) (x)), "n" (0))
+/* Some ColdFire architectures have a ff1 instruction supported via
+ __builtin_clz. */
+#elif defined (__mcfisaaplus__) || defined (__mcfisac__)
+#define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
+#define COUNT_LEADING_ZEROS_0 32
#endif
#endif /* mc68000 */
Index: gcc/config/m68k/m68k.h
===================================================================
--- gcc/config/m68k/m68k.h 2007-01-09 15:02:17.000000000 +0000
+++ gcc/config/m68k/m68k.h 2007-01-09 15:02:18.000000000 +0000
@@ -894,6 +894,9 @@ #define SLOW_BYTE_ACCESS 0
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+/* The ColdFire FF1 instruction returns 32 for zero. */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
+
#define STORE_FLAG_VALUE (-1)
#define Pmode SImode
Index: gcc/config/m68k/m68k.md
===================================================================
--- gcc/config/m68k/m68k.md 2007-01-09 15:02:18.000000000 +0000
+++ gcc/config/m68k/m68k.md 2007-01-09 15:02:18.000000000 +0000
@@ -3990,6 +3990,15 @@ (define_insn "abs<mode>2_cf"
return "f<FP:prec>abs%.<FP:prec> %1,%0";
})
+;; bit indexing instructions
+
+;; ColdFire ff1 instruction implements clz.
+(define_insn "clzsi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (clz:SI (match_operand:SI 1 "register_operand" "0")))]
+ "TARGET_ISAAPLUS || TARGET_ISAC"
+ "ff1 %0")
+
;; one complement instructions
;; "one_cmpldi2" is mainly here to help combine().