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Re: [PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug
- From: Peter Bergner <bergner at vnet dot ibm dot com>
- To: David Edelsohn <dje at watson dot ibm dot com>, Ulrich Weigand <ulrich dot weigand at de dot ibm dot com>
- Cc: gcc-patches at gcc dot gnu dot org, Michael Matz <matz at suse dot de>, Andrew Pinski <pinskia at gmail dot com>
- Date: Tue, 12 Dec 2006 14:03:46 -0600
- Subject: Re: [PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug
- References: <20061211183126.GA914@vervain.rchland.ibm.com> <200612112046.kBBKksV38062@makai.watson.ibm.com>
On Mon, Dec 11, 2006 at 03:46:54PM -0500, David Edelsohn wrote:
> This patch is okay, but please update the comment above the
> predicate explaining why accepting anything for reload_in_progress is
> necessary.
Just to be complete, here is the patch I tested which bootstrapped
and regtested with no failures on powerpc64-linux and running the
testsuite with both -m32 and -m64.
David & Uli, is this still ok to commit?
Peter
2006-12-12 Peter Bergner <bergner@vnet.ibm.com>
* reload1.c (eliminate_regs_in_insn): Merge the plus_src "else" and
the offset == 0 "then" clauses.
* config/rs6000/predicates.md (gpc_reg_operand): Check for
reload_in_progress.
Index: config/rs6000/predicates.md
===================================================================
--- config/rs6000/predicates.md (revision 119749)
+++ config/rs6000/predicates.md (working copy)
@@ -81,10 +81,13 @@
(and (match_code "const_int")
(match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
-;; Return 1 if op is a register that is not special.
+;; Return 1 if op is a register that is not special. We accept anything
+;; during reload_in_progress since eliminate_regs_in_insn() sometimes
+;; creates invalid insns which will be fixed up later in reload.
(define_predicate "gpc_reg_operand"
(and (match_operand 0 "register_operand")
- (match_test "(GET_CODE (op) != REG
+ (match_test "(reload_in_progress
+ || GET_CODE (op) != REG
|| (REGNO (op) >= ARG_POINTER_REGNUM
&& !XER_REGNO_P (REGNO (op)))
|| REGNO (op) < MQ_REGNO)
Index: reload1.c
===================================================================
--- reload1.c (revision 119749)
+++ reload1.c (working copy)
@@ -3098,7 +3098,7 @@ eliminate_regs_in_insn (rtx insn, int re
if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
to_rtx);
- if (offset == 0)
+ if (offset == 0 || plus_src)
{
int num_clobbers;
/* We assume here that if we need a PARALLEL with
@@ -3107,7 +3107,7 @@ eliminate_regs_in_insn (rtx insn, int re
There's not much we can do if that doesn't work. */
PATTERN (insn) = gen_rtx_SET (VOIDmode,
SET_DEST (old_set),
- to_rtx);
+ plus_constant (to_rtx, offset));
num_clobbers = 0;
INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
if (num_clobbers)
@@ -3120,26 +3120,6 @@ eliminate_regs_in_insn (rtx insn, int re
}
gcc_assert (INSN_CODE (insn) >= 0);
}
- /* If we have a nonzero offset, and the source is already
- a simple REG, the following transformation would
- increase the cost of the insn by replacing a simple REG
- with (plus (reg sp) CST). So try only when we already
- had a PLUS before. */
- else if (plus_src)
- {
- new_body = old_body;
- if (! replace)
- {
- new_body = copy_insn (old_body);
- if (REG_NOTES (insn))
- REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
- }
- PATTERN (insn) = new_body;
- old_set = single_set (insn);
-
- XEXP (SET_SRC (old_set), 0) = to_rtx;
- XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
- }
else
break;