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Re: [PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug

On Thu, 2006-12-07 at 16:52 -0600, Peter Bergner wrote:
> We end up in the modified code below with the "eliminated" insn now looking
> like:
> (insn:HI 176 157 267 4 (set (reg/f:SI 65 lr [265])
>         (plus:SI (reg/f:SI 1 1)
>             (const_int 12 [0xc]))) 79 {*addsi3_internal1} (nil)
>     (expr_list:REG_EQUIV (plus:SI (reg/f:SI 113 sfp)
>             (const_int 12 [0xc]))
>         (nil)))
> So we haven't eliminated the regs in the REG_EQUIV note.  We then die in
> the gcc_assert (INSN_CODE (insn) >= 0).  I thought it might be due to
> the REG_EQUIV not be "eliminate"'d before calling recog, but that doesn't
> seem to be the case, since I used to debugger to manually eliminate it
> before calling recog(), and we still end up dying.  Any idea what's
> wrong now?

We don't cause an extra reload to happen as you cannot set the lr via an
add.  But that instruction seems weird in general as why are we storing
r1+12 inside the lr when we can recalulate that when we would use lr.

Andrew Pinski

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