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Re: [patch] MIPS: 64bit floating point support for MIPS32R2


Richard Sandiford wrote:
David Ung <davidu@mips.com> writes:


Richard Sandiford wrote:


I'm still a little worried about that cannot_change_mode_class hunk;
do you know off-hand why it's needed?

hmm. If I still recall this correctly. The check (FP_INC > 1) is no longer valid for gp32+fp64, but there still needs a reg_classes_intersect_p (FP_REGS, class) check to ensure we ain't simply converting between 32bit integer and 64bit floats. The check at the end of the function will catch 32bit -> 64bit float, but not 64bit -> 32bit. It should allow pattens such as subreg:SI (reg:DF) or even the paradoxical subreg:DI (reg:SF) provided they fit. But subreg:SF (reg:DI) is a no no.


I'm probably being dense here, but why is it a no-no?  How is it
different from the -mgp64 -mfp64 case?


I am guessing here since I don't have a real example, so correct me if I am wrong,


In -mgp32 -mfp32, if you have

set (subreg:SF (reg:DI X) 0) (reg:SF Y)
set (subreg:SF (reg:DI X) 4) (reg:SF Z)

will mean allocation X to a float register eg $f0, and you get

set (reg:SF $f0) (reg:SF Y)
set (reg:SF $f1) (reg:SF Z)

in -mgp32 -mfp64:

set (reg:SF $f0) (reg:SF Y)
set (reg:SF ???) (reg:SF Z)

there just no patterns to match that, nor are
set (subreg:SF (reg:DI $f0) 4) ...

in -mgp64 -mfp64, would you even generate the above patterns?

Complex modes makes it more tricky. And O32 doesn't even defind how they are handled as argument / return values in 32/64 bit.

Another senarios is the code will stop

set (subreg:SI (reg:DF X) 0) ..
set (subreg:SI (reg:DF X) 4) ..

from X being allocated a float register, as there are no patterns to match and use the mthc1 instruction. (Side note, the mtc1 must occur before mthc1 in the instruction stream aswell)
As such, any 64bit conversion to/from float requires the use of mips_split_64bit_move to generate the patterns for m[f|t]hc1.


I am not sure if theres another way to work around it, I am open to suggestions.

David.


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