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Re: [patch] MIPS: 64bit floating point support for MIPS32R2
David Ung <firstname.lastname@example.org> writes:
> Richard Sandiford wrote:
>> I'm still a little worried about that cannot_change_mode_class hunk;
>> do you know off-hand why it's needed?
> hmm. If I still recall this correctly. The check (FP_INC > 1) is no
> longer valid for gp32+fp64, but there still needs a
> reg_classes_intersect_p (FP_REGS, class) check to ensure we ain't
> simply converting between 32bit integer and 64bit floats. The check
> at the end of the function will catch 32bit -> 64bit float, but not
> 64bit -> 32bit. It should allow pattens such as subreg:SI (reg:DF) or
> even the paradoxical subreg:DI (reg:SF) provided they fit. But
> subreg:SF (reg:DI) is a no no.
I'm probably being dense here, but why is it a no-no? How is it
different from the -mgp64 -mfp64 case?
The check at the end of the function is to do with the invariant that
SImode registers must be stored in sign-extended form if TARGET_64BIT.
That doesn't apply here; indeed, your patch should probably add
"TARGET_64BIT &&". ;)
>> mips_class_max_nregs might also need changing btw.
> I guess we should add something like
> if (class == FP_REGS)
> return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
Yeah, given that we simply want to decrease the return value for
FP regs, while keeping the union classes the same, I think that
should cover it. I suggest changing the comment to something like:
The rules are as follows:
- UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
- ST_REGS are always hold CCmode values, and CCmode values are
considered to be 4 bytes wide.
All other register classes are covered by UNITS_PER_WORD. Note that
this is true even for unions of integer and float registers when the
latter are smaller than the former. The only supported combination
in which case this occurs is -mgp64 -msingle-float, which has 64-bit
words but 32-bit float registers. A word-based calculation is correct
in that case since -msingle-float disallows multi-FPR values. */