Re: [patch]: MIPS: Add mfhc1/mthc1 patterns for MIPS32R2 64bit fpu

[Richard Sandiford <richard at codesourcery dot com>]

David Ung <davidu@mips.com> writes:
> +;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
> +;; value in the low word.
> +(define_insn "mthc1"
> +  [(set (match_operand 0 "register_operand" "=f")
> +	(unspec [(match_operand:SI 1 "general_operand" "dJ")
> +		 (match_operand 2 "register_operand" "0")]
> +		UNSPEC_MTHC1))]
> +  "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
> +  "mthc1\t%z1,%0"
> +  [(set_attr "type"	"xfer")
> +   (set_attr "mode"	"SF")])
> +
> +;; Move high word of operand 1 to operand 0 using mfhc1.  The corresponding
> +;; low-word move is done in the normal way.
> +(define_insn "mfhc1"
> +  [(set (match_operand:SI 0 "register_operand" "=d")
> +	(unspec:SI [(match_operand 1 "register_operand" "f")]
> +		   UNSPEC_MFHC1))]
> +  "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
> +  "mfhc1\t%0,%1"
> +  [(set_attr "type"	"xfer")
> +   (set_attr "mode"	"SF")])

My comments about load_df* modes apply to this too.  And given that
your previous patch passed tests even without this patch, I really
would like to see a testcase that exercises this path, both for
DFmode and DImode.

Could you combine and resubmit the patches after taking my comments
about your other patch into account?

Richard