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Re: Ping Patch: PR target/24879: SSE3 intrinsic bug
On Thu, May 04, 2006 at 07:06:27AM -0700, H. J. Lu wrote:
> On Wed, May 03, 2006 at 08:50:27PM -0700, Ian Lance Taylor wrote:
> > "H. J. Lu" <hjl@lucon.org> writes:
> >
> > > --- gcc/config/i386/i386.c.64bit 2006-05-03 06:22:19.000000000 -0700
> > > +++ gcc/config/i386/i386.c 2006-05-03 06:39:59.000000000 -0700
> > > @@ -14915,8 +14915,8 @@ ix86_init_mmx_sse_builtins (void)
> > > tree void_ftype_unsigned_unsigned
> > > = build_function_type_list (void_type_node, unsigned_type_node,
> > > unsigned_type_node, NULL_TREE);
> > > - tree void_ftype_pcvoid_unsigned_unsigned
> > > - = build_function_type_list (void_type_node, const_ptr_type_node,
> > > + tree void_ftype_unsigned_unsigned_unsigned
> > > + = build_function_type_list (void_type_node, unsigned_type_node,
> > > unsigned_type_node, unsigned_type_node,
> > > NULL_TREE);
> >
> > I don't mean to cause (even more) trouble, but why did you change the
> > type of the first argument? Isn't void* correct? I would expect that
> > there would still be two monitor insns in the md file, one with a
> > DImode first argument and one with an SImode argument. Then you would
> > emit one or the other in ix86_expand_builtin. Does that make sense?
>
> The 64bit versions take 64bit registers. But the current implementation
> only checks the lower 32bit. I would prefer we treat 32bit/64bit
> version identical by making all arguments 32bit or make 64bit version
> with all arguments 64bit. It is odd to have a hybrid 64bit.
>
>
Maybe the hybrid 64bit monitor is better. Here is the updated patch.
H.J.
----
gcc/
2006-05-04 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* config/i386/pmmintrin.h (_mm_monitor): Remove macro. Use
inline function.
(_mm_mwait): Likewise.
* config/i386/sse.md (sse3_mwait): Replace "mwait\t%0, %1" with
"mwait".
(sse3_monitor): Make it 32bit only.
(sse3_monitor64): New. 64bit monitor.
gcc/testsuite/
2006-05-04 H.J. Lu <hongjiu.lu@intel.com>
PR target/24879
* gcc.target/i386/monitor.c: New file.
--- gcc/config/i386/pmmintrin.h.64bit 2005-11-04 14:13:48.000000000 -0800
+++ gcc/config/i386/pmmintrin.h 2006-05-04 08:42:42.000000000 -0700
@@ -1,4 +1,4 @@
-/* Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
+/* Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
This file is part of GCC.
@@ -25,7 +25,7 @@
Public License. */
/* Implemented from the specification included in the Intel C++ Compiler
- User Guide and Reference, version 8.0. */
+ User Guide and Reference, version 9.0. */
#ifndef _PMMINTRIN_H_INCLUDED
#define _PMMINTRIN_H_INCLUDED
@@ -110,7 +110,6 @@ _mm_lddqu_si128 (__m128i const *__P)
return (__m128i) __builtin_ia32_lddqu ((char const *)__P);
}
-#if 0
static __inline void __attribute__((__always_inline__))
_mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
{
@@ -122,10 +121,6 @@ _mm_mwait (unsigned int __E, unsigned in
{
__builtin_ia32_mwait (__E, __H);
}
-#else
-#define _mm_monitor(P, E, H) __builtin_ia32_monitor ((P), (E), (H))
-#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H))
-#endif
#endif /* __SSE3__ */
--- gcc/config/i386/sse.md.64bit 2006-05-03 12:04:28.000000000 -0700
+++ gcc/config/i386/sse.md 2006-05-04 08:47:00.000000000 -0700
@@ -3972,7 +3972,10 @@
(match_operand:SI 1 "register_operand" "c")]
UNSPECV_MWAIT)]
"TARGET_SSE3"
- "mwait\t%0, %1"
+;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.
+;; Since 32bit register operands are implicitly zero extended to 64bit,
+;; we only need to set up 32bit registers.
+ "mwait"
[(set_attr "length" "3")])
(define_insn "sse3_monitor"
@@ -3980,10 +3983,22 @@
(match_operand:SI 1 "register_operand" "c")
(match_operand:SI 2 "register_operand" "d")]
UNSPECV_MONITOR)]
- "TARGET_SSE3"
+ "TARGET_SSE3 && !TARGET_64BIT"
"monitor\t%0, %1, %2"
[(set_attr "length" "3")])
+(define_insn "sse3_monitor64"
+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
+ (match_operand:SI 1 "register_operand" "c")
+ (match_operand:SI 2 "register_operand" "d")]
+ UNSPECV_MONITOR)]
+ "TARGET_SSE3 && TARGET_64BIT"
+;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
+;; RCX and RDX are used. Since 32bit register operands are implicitly
+;; zero extended to 64bit, we only need to set up 32bit registers.
+ "monitor"
+ [(set_attr "length" "3")])
+
;; MNI
(define_insn "mni_phaddwv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- gcc/testsuite/gcc.target/i386/monitor.c.64bit 2006-05-03 12:04:28.000000000 -0700
+++ gcc/testsuite/gcc.target/i386/monitor.c 2006-05-03 12:04:28.000000000 -0700
@@ -0,0 +1,27 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -msse3" } */
+
+/* Verify that they work in both 32bit and 64bit. */
+
+#include <pmmintrin.h>
+
+void
+foo (char *p, int x, int y, int z)
+{
+ _mm_monitor (p, y, x);
+ _mm_mwait (z, y);
+}
+
+void
+bar (char *p, long x, long y, long z)
+{
+ _mm_monitor (p, y, x);
+ _mm_mwait (z, y);
+}
+
+void
+foo1 (char *p)
+{
+ _mm_monitor (p, 0, 0);
+ _mm_mwait (0, 0);
+}