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[PATCH, ARM]: Add special case patterns for min or max with zero.
- From: Richard Earnshaw <Richard dot Earnshaw at buzzard dot freeserve dot co dot uk>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
- Date: Thu, 26 Jan 2006 08:03:37 +0000
- Subject: [PATCH, ARM]: Add special case patterns for min or max with zero.
On ARM it is possible to implement smax:SI (x, 0) and smin:SI (x, 0) in a
single instruction and without clobbering the condition code register,
which is 1 or 2 instructions shorter than the existing code generated.
This patch adds patterns to achieve that.
Tested on arm-elf with no regressions.
2006-01-26 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.md (smaxsi3, sminsi3): Convert to define_expand.
(smax_insn, smin_insn, smax_0, smin_0): New.
*** config/arm/arm.md (revision 110269)
--- config/arm/arm.md (local)
*************** (define_split
*** 2473,2504 ****
;; Minimum and maximum insns
! (define_insn "smaxsi3"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
! (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
! (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movlt\\t%0, %2
- cmp\\t%1, %2\;movge\\t%0, %1
cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
[(set_attr "conds" "clob")
! (set_attr "length" "8,8,12")]
)
! (define_insn "sminsi3"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
! (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
! (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movge\\t%0, %2
- cmp\\t%1, %2\;movlt\\t%0, %1
cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
[(set_attr "conds" "clob")
! (set_attr "length" "8,8,12")]
)
(define_insn "umaxsi3"
--- 2473,2556 ----
;; Minimum and maximum insns
! (define_expand "smaxsi3"
! [(parallel [
! (set (match_operand:SI 0 "s_register_operand" "")
! (smax:SI (match_operand:SI 1 "s_register_operand" "")
! (match_operand:SI 2 "arm_rhs_operand" "")))
! (clobber (reg:CC CC_REGNUM))])]
! "TARGET_ARM"
! "
! if (operands[2] == const0_rtx)
! {
! /* No need for a clobber of the condition code register here. */
! emit_insn (gen_rtx_SET (VOIDmode, operands[0],
! gen_rtx_SMAX (SImode, operands[1],
! operands[2])));
! DONE;
! }
! ")
!
! (define_insn "*smax_0"
! [(set (match_operand:SI 0 "s_register_operand" "=r")
! (smax:SI (match_operand:SI 1 "s_register_operand" "r")
! (const_int 0)))]
! "TARGET_ARM"
! "bic%?\\t%0, %1, %1, asr #31"
! [(set_attr "predicable" "yes")]
! )
!
! (define_insn "*smax_insn"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r")
! (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
! (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movlt\\t%0, %2
cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
[(set_attr "conds" "clob")
! (set_attr "length" "8,12")]
)
! (define_expand "sminsi3"
! [(parallel [
! (set (match_operand:SI 0 "s_register_operand" "")
! (smin:SI (match_operand:SI 1 "s_register_operand" "")
! (match_operand:SI 2 "arm_rhs_operand" "")))
! (clobber (reg:CC CC_REGNUM))])]
! "TARGET_ARM"
! "
! if (operands[2] == const0_rtx)
! {
! /* No need for a clobber of the condition code register here. */
! emit_insn (gen_rtx_SET (VOIDmode, operands[0],
! gen_rtx_SMIN (SImode, operands[1],
! operands[2])));
! DONE;
! }
! ")
!
! (define_insn "*smin_0"
! [(set (match_operand:SI 0 "s_register_operand" "=r")
! (smin:SI (match_operand:SI 1 "s_register_operand" "r")
! (const_int 0)))]
! "TARGET_ARM"
! "and%?\\t%0, %1, %1, asr #31"
! [(set_attr "predicable" "yes")]
! )
!
! (define_insn "*smin_insn"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r")
! (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
! (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"@
cmp\\t%1, %2\;movge\\t%0, %2
cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
[(set_attr "conds" "clob")
! (set_attr "length" "8,12")]
)
(define_insn "umaxsi3"