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[MT]: Add ms2 multilib
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Aldy Hernandez <aldyh at redhat dot com>
- Date: Tue, 13 Dec 2005 09:57:59 +0000
- Subject: [MT]: Add ms2 multilib
I've installed this patch to add ms2 multilibs. I needed to fix a bug in the
loop reorg code, because ms1-16-003 can now generate dbnz for doloop_end, but we
don't want to go and rearrange loops on that target. I fixed up the other
places where we directly checked ms1_cpu while I was at it.
built with an mt-elf cross compiler.
Now I can continue with the renaming ...
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2005-12-13 Nathan Sidwell <nathan@codesourcery.com>
* config/mt/t-mt (MULTILIB_OPTIONS): Add ms2
(MULTILIB_DIRNAMES): Add ms2. Prefix ms1 dirs with 'ms1'.
* config/mt/mt.c (ms1_final_prescan): Use TARGET_MS2,
TARGET_MS1_64_001 appropriately.
(ms1_machine_reorg): Use TARGET_MS2.
Index: config/mt/t-mt
===================================================================
--- config/mt/t-mt (revision 108403)
+++ config/mt/t-mt (working copy)
@@ -59,8 +59,8 @@ crtn.o: $(srcdir)/config/mt/crtn.asm $(G
# See gcc/genmultilib, gcc/gcc.texi and gcc/tm.texi for a
# description of the options and their values.
#
-MULTILIB_OPTIONS = march=ms1-64-001/march=ms1-16-002/march=ms1-16-003
-MULTILIB_DIRNAMES = 64-001 16-002 16-003
+MULTILIB_OPTIONS = march=ms1-64-001/march=ms1-16-002/march=ms1-16-003/march=ms2
+MULTILIB_DIRNAMES = ms1-64-001 ms1-16-002 ms1-16-003 ms2
# MULTILIB_MATCHES =
# MULTILIB_EXCEPTIONS =
# MULTILIB_EXTRA_OPTS =
Index: config/mt/mt.c
===================================================================
--- config/mt/mt.c (revision 108403)
+++ config/mt/mt.c (working copy)
@@ -221,7 +221,7 @@ ms1_final_prescan_insn (rtx insn,
ms1_nop_reasons = "";
/* ms2 constraints are dealt with in reorg. */
- if (ms1_cpu == PROCESSOR_MS2)
+ if (TARGET_MS2)
return;
/* Only worry about real instructions. */
@@ -257,7 +257,7 @@ ms1_final_prescan_insn (rtx insn,
case TYPE_STORE:
/* Avoid consecutive memory operation. */
if ((prev_attr == TYPE_LOAD || prev_attr == TYPE_STORE)
- && ms1_cpu == PROCESSOR_MS1_64_001)
+ && TARGET_MS1_64_001)
{
ms1_nops_required = 1;
ms1_nop_reasons = "consecutive mem ops";
@@ -279,8 +279,7 @@ ms1_final_prescan_insn (rtx insn,
case TYPE_BRANCH:
if (insn_dependent_p (prev_i, insn))
{
- if (prev_attr == TYPE_ARITH
- && ms1_cpu == PROCESSOR_MS1_64_001)
+ if (prev_attr == TYPE_ARITH && TARGET_MS1_64_001)
{
/* One cycle of delay between arith
instructions and branch dependent on arith. */
@@ -291,7 +290,7 @@ ms1_final_prescan_insn (rtx insn,
{
/* Two cycles of delay are required
between load and dependent branch. */
- if (ms1_cpu == PROCESSOR_MS1_64_001)
+ if (TARGET_MS1_64_001)
ms1_nops_required = 2;
else
ms1_nops_required = 1;
@@ -2465,13 +2464,13 @@ ms1_reorg_hazard (void)
static void
ms1_machine_reorg (void)
{
- if (cfun->machine->has_loops)
+ if (cfun->machine->has_loops && TARGET_MS2)
ms1_reorg_loops (dump_file);
if (ms1_flag_delayed_branch)
dbr_schedule (get_insns (), dump_file);
- if (ms1_cpu == PROCESSOR_MS2)
+ if (TARGET_MS2)
ms1_reorg_hazard ();
}