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[Bug middle-end/24950] ICE in operand_subword_force
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 21 Nov 2005 18:32:49 +1030
- Subject: [Bug middle-end/24950] ICE in operand_subword_force
:ADDPATCH middle-end:
Dale Johannesen's newly added testcase fails on powerpc64-linux with an
ICE, because the fix Dale applied for MEMs doesn't trigger for us. We
have a misaligned 64-bit field. Code a little below the place I'm
patching here loads a "bestmode" reg from the MEM and attempts to insv
the "fieldmode" value. "bestmode" is taken from the MEM, which is
SImode, while "fieldmode" is DImode. Needless to say, this doesn't work
very well.
PR middle-end/24950
* expmed.c (store_bit_field): Don't attempt to insv a field
larger than the reg.
Bootstrap and regression tests in progress. OK everywhere? This is a
regression from gcc-3.3, which compiles correctly because
store_bit_field gets passed a BLKmode MEM destination.
Index: gcc/expmed.c
===================================================================
--- gcc/expmed.c (revision 107280)
+++ gcc/expmed.c (working copy)
@@ -640,7 +640,11 @@ store_bit_field (rtx str_rtx, unsigned H
= get_best_mode (bitsize, bitnum, MEM_ALIGN (op0), maxmode,
MEM_VOLATILE_P (op0));
else
- bestmode = GET_MODE (op0);
+ {
+ bestmode = GET_MODE (op0);
+ if (GET_MODE_SIZE (bestmode) < GET_MODE_SIZE (fieldmode))
+ bestmode = VOIDmode;
+ }
if (bestmode == VOIDmode
|| (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
--
Alan Modra
IBM OzLabs - Linux Technology Centre