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[PATCH] PR 24861: Fix invalid split pattern when compiling for EP9312
- From: Richard Earnshaw <Richard dot Earnshaw at buzzard dot freeserve dot co dot uk>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
- Date: Wed, 16 Nov 2005 22:37:03 +0000
- Subject: [PATCH] PR 24861: Fix invalid split pattern when compiling for EP9312
There was a split pattern that was converting a set of a floating point
value
into a set of an integer value. This doesn't match anything if the
register
being set is a Maverick Co-pro register, and in general we only want to do
this
if setting an ARM core register. Having restricted the pattern in this
way,
the extra constraint that disabled the pattern for the FPA is no-longer
relevant.
Tested on an arm-elf cross and by compiling some code for -mcpu=ep9312
-mhard-float
2005-11-16 Richard Earnshaw <richard.earnshaw@arm.com>
PR target/24861
* arm.md (split for movsf with immediate): Restrict split to insns
that set a general register.
*** arm.md (revision 106936)
--- arm.md (local)
*************** (define_expand "movsf"
*** 5137,5147 ****
"
)
(define_split
! [(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "immediate_operand" ""))]
"TARGET_ARM
- && !(TARGET_HARD_FLOAT && TARGET_FPA)
&& reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
[(set (match_dup 2) (match_dup 3))]
--- 5137,5148 ----
"
)
+ ;; Transform a floating-point move of a constant into a core register into
+ ;; an SImode operation.
(define_split
! [(set (match_operand:SF 0 "arm_general_register_operand" "")
(match_operand:SF 1 "immediate_operand" ""))]
"TARGET_ARM
&& reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
[(set (match_dup 2) (match_dup 3))]