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ARM: Add a missing clobber in longlong.h


Mark Mitchell found an old bug in the glibc copy of this header, which is
also present in GCC (for __udivmoddi4).

The attached patch has no effect on the generated code for libgcc,
so I've not committed it to HEAD; I will when HEAD is open for
non-regression bug fixes.  I've committed it to csl-arm-branch.

-- 
Daniel Jacobowitz
CodeSourcery, LLC

2005-10-10  Mark Mitchell  <mark@codesourcery.com>
	    Daniel Jacobowitz  <dan@codesourcery.com>

	* longlong.h (add_ssaaaa): Clobber condition code register
	in ARM version.
	(sub_ddmmss): Likewise.
	(umul_ppmm): Likewise.

Index: longlong.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/longlong.h,v
retrieving revision 1.39.4.2
diff -u -p -r1.39.4.2 longlong.h
--- longlong.h	16 Aug 2004 17:13:09 -0000	1.39.4.2
+++ longlong.h	10 Oct 2005 20:24:09 -0000
@@ -194,7 +194,7 @@ UDItype __umulsidi3 (USItype, USItype);
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
-	     "rI" ((USItype) (bl)))
+	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
 	   : "=r" ((USItype) (sh)),					\
@@ -202,7 +202,7 @@ UDItype __umulsidi3 (USItype, USItype);
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
-	     "rI" ((USItype) (bl)))
+	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define umul_ppmm(xh, xl, a, b) \
 {register USItype __t0, __t1, __t2;					\
   __asm__ ("%@ Inlined umul_ppmm\n"					\
@@ -222,7 +222,7 @@ UDItype __umulsidi3 (USItype, USItype);
 	     "=r" ((USItype) (xl)),					\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
-	     "r" ((USItype) (b)));}
+	     "r" ((USItype) (b)) __CLOBBER_CC );}
 #define UMUL_TIME 20
 #define UDIV_TIME 100
 #endif /* __arm__ */


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