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Re: [PATCH] Exploiting dual mode operation, implementation.
- From: Mircea Namolaru <NAMOLARU at il dot ibm dot com>
- To: Richard Henderson <rth at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org, Leehod Baruch <LEEHOD at il dot ibm dot com>, Leehod Baruch <sleehodb at t2 dot technion dot ac dot il>, stevenb at suse dot de
- Date: Wed, 3 Aug 2005 17:19:52 +0200
- Subject: Re: [PATCH] Exploiting dual mode operation, implementation.
The algorithm have been designed to deal with 32-bit computations on
64-bit architectures. In this case sign extension instructions are
generated in order to preserve the correctness and this may cause serious
performance overhead. An attempt to solve this problem is described in
"Effective Sign Extension Elimination" by Kawahito M., Komatsu H.,
Nakatani T, PLDI 2002. In our opinion, our approach is an improvement
over their algorithm and it is simpler to implement.
The algorithm will work for A-bit computation on B-bit architectures
(where B is a larger mode then A). It doesn't seem that it easy to extend
it to webs having a mixture of different B sub-modes computations. We will
try, but for the moment we don't have a solution for this. However in his
current form the algorithm succeeds in providing a solution to the problem
for which it was originally designed (i.e 32-bit computation on 64-bit
architectures). And this is exactly the case when many redundant sign
extend instructions are generated.
The algorithm was presented in way that mirrors the current
implementation. We wanted to use combine and gcse as a kind of black
boxes, our single task being to bring the code to a form suitable to these
optimizations. Unfortunately the things proved to be more difficult then
we thought .... we are working now at a different implementation.
Mircea