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Re: RFC: MIPS clones without lwl/lwr/swl/swr
- From: Eric Christopher <echristo at redhat dot com>
- To: Richard Sandiford <rsandifo at redhat dot com>
- Cc: Marek Michalkiewicz <marekm at amelek dot gda dot pl>, gcc-patches at gcc dot gnu dot org
- Date: Mon, 16 May 2005 16:17:46 -0700
- Subject: Re: RFC: MIPS clones without lwl/lwr/swl/swr
- References: <20050513145612.GA17580@amelek.gda.pl> <firstname.lastname@example.org>
> Looks good to me.
> The MIPS port usually guards this sort of instruction selection with an
> ISA_HAS_* macro (ISA_HAS_COND_TRAP, ISA_HAS_CLZ_CLO, etc.). One thing
> I'd like to see is a new ISA_HAS_* macro to say whether lwl/lwr,
> etc. are available. The macro would be false if your new option is
> passed and would also be false for TARGET_MIPS16. If at some point
> in the future, -march is extended to support a processor without the
> patented instructions, the macro would be false when generating code
> for that processor.
Actually I'd prefer ISA_HAS_* for the -march and !TARGET_MIPS16 case and
use GENERATE_* for whether or not we should generate it. i.e.
#define ISA_HAS_PATENT_FOO (!TARGET_MIPS16 \
&& !TARGET_LEXRA* )
(or whatever we decide for the lexra chips or whatever doesn't have
#define GENERATE_PATENT_FOO (TARGET_PATENTFOO && ISA_HAS_PATENT_FOO)
But it is just naming issues and such. Not horribly important. :)