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Re: RFC: MIPS clones without lwl/lwr/swl/swr


> Looks good to me.
> 

Ditto.

> The MIPS port usually guards this sort of instruction selection with an
> ISA_HAS_* macro (ISA_HAS_COND_TRAP, ISA_HAS_CLZ_CLO, etc.).  One thing
> I'd like to see is a new ISA_HAS_* macro to say whether lwl/lwr,
> etc. are available.  The macro would be false if your new option is
> passed and would also be false for TARGET_MIPS16.  If at some point
> in the future, -march is extended to support a processor without the
> patented instructions, the macro would be false when generating code
> for that processor.

Actually I'd prefer ISA_HAS_* for the -march and !TARGET_MIPS16 case and
use GENERATE_* for whether or not we should generate it. i.e.

#define ISA_HAS_PATENT_FOO (!TARGET_MIPS16 \
			     && !TARGET_LEXRA* ) 

(or whatever we decide for the lexra chips or whatever doesn't have
them)

and then

#define GENERATE_PATENT_FOO (TARGET_PATENTFOO && ISA_HAS_PATENT_FOO)

But it is just naming issues and such. Not horribly important. :)

-eric


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