This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: RFC: MIPS clones without lwl/lwr/swl/swr

Thiemo Seufer <> writes:
>> Looks good to me.
>> The MIPS port usually guards this sort of instruction selection with an
>> ISA_HAS_* macro (ISA_HAS_COND_TRAP, ISA_HAS_CLZ_CLO, etc.).  One thing
>> I'd like to see is a new ISA_HAS_* macro to say whether lwl/lwr,
>> etc. are available.
> I don't think those should be handled as a separate ISA, for several
> reasons:
> [...]

I think you misunderstand.  I'm not suggesting a separate ISA in the
enum processor_type sense.  I'm just suggesting having a macro that
says "do the current command-line flags allow me to use lwl?"  Look
at the definitions of the existing ISA_HAS_* macros and the ways
that they are used.

> A GENERATE_PATENTED macro seems to be a better choice.

Well, this is just a naming issue then.  We're both talking about having
a macro that says "can I generate instruction X".  And that's exactly
what the existing ISA_HAS_* macros are for.  We can certainly argue
about what does and doesn't constitute an "ISA", and (for example)
whether "-mips3 -mpatent-free" selects a different ISA than plain
"-mips3", or whether MIPS16 code uses a different ISA from non-MIPS16
code.  IMO, they do, but arguing about it is just pedantry...


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]