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[s390] patch: merge mem patterns using recent macro update


Hi,

after a recent patch concerning mode macro attributes, it is now
possible to merge DI and SI versions of the movmem, clrmem, and cmpmem
patterns. This is a patch do this.

Bootstrapped and regtested an s390 and s390x. insn-emit.c does not
change.
Ok to apply?


2005-05-12  Adrian Straetling  <straetling@de.ibm.com>

	* gcc/config/s390.md: ("DBL"): New mode attribute.
	("*movmem_long_64", "*movmem_long_31"): Merge to "*movmem_long".
	("*clrmem_long_64", "*clrmem_long_31"): Merge to "*clrmem_long".
	("*cmpmem_long_64", "*cmpmem_long_31"): Merge to "*cmpmem_long".


Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig	2005-05-11 14:06:05.000000000 +0200
--- gcc/config/s390/s390.md	2005-05-11 19:37:15.821486453 +0200
***************
*** 329,334 ****
--- 329,338 ----
  ;; HImode and "llgc" in QImode.
  (define_mode_attr hc [(HI "h") (QI "c")])
  
+ ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
+ ;; in SImode.
+ (define_mode_attr DBL [(DI "TI") (SI "DI")])
+ 
  ;; Maximum unsigned integer that fits in MODE.
  (define_mode_attr max_uint [(HI "65535") (QI "255")])
  
***************
*** 1897,1924 ****
    operands[3] = reg1;
  })
  
! (define_insn "*movmem_long_64"
!   [(clobber (match_operand:TI 0 "register_operand" "=d"))
!    (clobber (match_operand:TI 1 "register_operand" "=d"))
!    (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
!         (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
!    (use (match_dup 2))
!    (use (match_dup 3))
!    (clobber (reg:CC CC_REGNUM))]
!   "TARGET_64BIT"
!   "mvcle\t%0,%1,0\;jo\t.-4"
!   [(set_attr "length" "8")
!    (set_attr "type" "vs")])
! 
! (define_insn "*movmem_long_31"
!   [(clobber (match_operand:DI 0 "register_operand" "=d"))
!    (clobber (match_operand:DI 1 "register_operand" "=d"))
!    (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
!         (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
     (use (match_dup 2))
     (use (match_dup 3))
     (clobber (reg:CC CC_REGNUM))]
!   "!TARGET_64BIT"
    "mvcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])
--- 1901,1915 ----
    operands[3] = reg1;
  })
  
! (define_insn "*movmem_long"
!   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
!    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
!    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
!         (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
     (use (match_dup 2))
     (use (match_dup 3))
     (clobber (reg:CC CC_REGNUM))]
!   ""
    "mvcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])
***************
*** 2037,2062 ****
    operands[2] = reg1;
  })
  
! (define_insn "*clrmem_long_64"
!   [(clobber (match_operand:TI 0 "register_operand" "=d"))
!    (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
          (const_int 0))
     (use (match_dup 2))
!    (use (match_operand:TI 1 "register_operand" "d"))
     (clobber (reg:CC CC_REGNUM))]
!   "TARGET_64BIT"
!   "mvcle\t%0,%1,0\;jo\t.-4"
!   [(set_attr "length" "8")
!    (set_attr "type" "vs")])
! 
! (define_insn "*clrmem_long_31"
!   [(clobber (match_operand:DI 0 "register_operand" "=d"))
!    (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
!         (const_int 0))
!    (use (match_dup 2))
!    (use (match_operand:DI 1 "register_operand" "d"))
!    (clobber (reg:CC CC_REGNUM))]
!   "!TARGET_64BIT"
    "mvcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])
--- 2028,2041 ----
    operands[2] = reg1;
  })
  
! (define_insn "*clrmem_long"
!   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
!    (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
          (const_int 0))
     (use (match_dup 2))
!    (use (match_operand:<DBL> 1 "register_operand" "d"))
     (clobber (reg:CC CC_REGNUM))]
!   ""
    "mvcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])
***************
*** 2180,2207 ****
    operands[3] = reg1;
  })
  
! (define_insn "*cmpmem_long_64"
!   [(clobber (match_operand:TI 0 "register_operand" "=d"))
!    (clobber (match_operand:TI 1 "register_operand" "=d"))
     (set (reg:CCU CC_REGNUM)
!         (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
!                      (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
     (use (match_dup 2))
     (use (match_dup 3))]
!   "TARGET_64BIT"
!   "clcle\t%0,%1,0\;jo\t.-4"
!   [(set_attr "length" "8")
!    (set_attr "type" "vs")])
! 
! (define_insn "*cmpmem_long_31"
!   [(clobber (match_operand:DI 0 "register_operand" "=d"))
!    (clobber (match_operand:DI 1 "register_operand" "=d"))
!    (set (reg:CCU CC_REGNUM)
!         (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
!                      (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
!    (use (match_dup 2))
!    (use (match_dup 3))]
!   "!TARGET_64BIT"
    "clcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])
--- 2159,2173 ----
    operands[3] = reg1;
  })
  
! (define_insn "*cmpmem_long"
!   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
!    (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
     (set (reg:CCU CC_REGNUM)
!         (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
!                      (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
     (use (match_dup 2))
     (use (match_dup 3))]
!   ""
    "clcle\t%0,%1,0\;jo\t.-4"
    [(set_attr "length" "8")
     (set_attr "type" "vs")])



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