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Re: [Patch] MIPS - Add 3 operand mul as new attribute to machinedescription.
> > * config/mips/mips.md ("type"): Add new attribute for a 3 operand
> > multiply.
> > ("mulsi3_mult3"): Set attribute to imul3.
> > ("muldi3_mult3"): Similarly.
>
> There are a few other three-operand multiplication patterns too.
> Grep for imul in mips.md. "may_clobber_hilo" should also be
> true for imul3. The patch looks good otherwise.
yes. I was abit nervious about making some of the other patterns imul3
as leaving then as imul would be a safe thing to do. But I guess the
muls patterns are really imul3 and there's no harm changing it since the
pipeline desc treats them as the same thing (for now).
> For the record (since you didn't mention this explicitly): some of the
> pipeline descriptions are using match_operand to differentiate between
> two- and three-operand multiplications and should probably be tweaked
> after this patch. But that sort of change is better done separately
> (and I'll try to do it myself... sometime ;). Simply changing "imul"
> to "imul,imul3" (like you do here) will not alter the DFA behaviour
> in any way and is the right thing for the initial "imul3" patch to do.
agreed.
David.
ok. Here is the new patch.
2005-05-11 David Ung <davidu@mips.com>
* config/mips/mips.md ("type"): Add new attribute for a 3 operand
multiply.
("length", "hazard", "may_clobber_hilo"): Check for imul3.
("mulsi3_mult3", "muldi3_mult3", "mul<mode>3_r4000", "*muls")
("<u>mulsidi3_32bit_r4000", "*<u>mulsidi3_64bit")
("<su>mulsi3_highpart_mulhi_internal")
("*<su>mulsi3_highpart_neg_mulhi_internal"): Set attr to imul3.
* config/mips/24k.md ("r24k_int_mul3"): Enable this reservation
for a 3 operand mul and its bypasses.
* config/mips/3000.md ("r3k_imul"): Add imul3 to reservations.
* config/mips/4000.md ("r4k_imul"): Similarly.
* config/mips/4100.md ("r4100_imul_si", "r4100_imul_di"): ..
* config/mips/4130.md ("vr4130_class", "vr4130_mulsi")
("vr4130_muldi"): ..
* config/mips/4300.md ("r4300_imul_si", "r4300_imul_di"): ..
* config/mips/4600.md ("r4600_imul", "r4650_imul"): ..
* config/mips/5000.md ("r5k_imul_si", "r5k_imul_di"): ..
* config/mips/5400.md ("ir_vr54_imul_si", "ir_vr54_imul_di")
("ir_vr54_imadd_si"): ..
* config/mips/5500.md ("ir_vr55_imul_si", "ir_vr55_imul_di"): ..
* config/mips/7000.md ("rm7_impy_si_mult", "rm7_impy_si_mul")
("rm7_impy_di"): ..
* config/mips/9000.md ("rm9k_mulsi", "rm9k_muldi"): ..
* config/mips/generic.md ("generic_imul"): ..
* config/mips/sb1.md ("ir_sb1_mulsi", "ir_sb1_muldi"): ..
* config/mips/sr71k.md ("ir_sr70_imul_si", "ir_sr70_imul_di"): ..
Index: config/mips/24k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/24k.md,v
retrieving revision 1.1
diff -c -3 -r1.1 24k.md
*** config/mips/24k.md 9 May 2005 11:43:48 -0000 1.1
--- config/mips/24k.md 11 May 2005 11:44:07 -0000
***************
*** 87,98 ****
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mul - delivers result to gpr in 5 cycles
! ;; (disabled for now until we introduce the 3 operand mul into the general
! ;; patterns).
! ;;(define_insn_reservation "r24k_int_mul3" 5
! ;; (and (eq_attr "cpu" "24k,24kx")
! ;; (eq_attr "type" "imul3"))
! ;; "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mfhilo" 5
--- 87,96 ----
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mul - delivers result to gpr in 5 cycles
! (define_insn_reservation "r24k_int_mul3" 5
! (and (eq_attr "cpu" "24k,24kx")
! (eq_attr "type" "imul3"))
! "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mfhilo" 5
***************
*** 186,194 ****
;; mul3->next use : 5 cycles (default)
;; mul3->l/s base : 6 cycles
;; mul3->prefetch : 6 cycles
! ;;(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
! ;;(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
! ;;(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
;; mfhilo->next use : 5 cycles (default)
;; mfhilo->l/s base : 6 cycles
--- 184,192 ----
;; mul3->next use : 5 cycles (default)
;; mul3->l/s base : 6 cycles
;; mul3->prefetch : 6 cycles
! (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
! (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
! (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
;; mfhilo->next use : 5 cycles (default)
;; mfhilo->l/s base : 6 cycles
Index: config/mips/3000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/3000.md,v
retrieving revision 1.4
diff -c -3 -r1.4 3000.md
*** config/mips/3000.md 18 Aug 2004 23:45:30 -0000 1.4
--- config/mips/3000.md 11 May 2005 11:44:07 -0000
***************
*** 29,35 ****
(define_insn_reservation "r3k_imul" 12
(and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "imul,imadd"))
"imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
--- 29,35 ----
(define_insn_reservation "r3k_imul" 12
(and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
Index: config/mips/4000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/4000.md,v
retrieving revision 1.1
diff -c -3 -r1.1 4000.md
*** config/mips/4000.md 12 Jul 2004 05:21:29 -0000 1.1
--- config/mips/4000.md 11 May 2005 11:44:07 -0000
***************
*** 24,30 ****
(define_insn_reservation "r4k_imul" 10
(and (eq_attr "cpu" "r4000")
! (eq_attr "type" "imul,imadd"))
"imuldiv*10")
(define_insn_reservation "r4k_idiv" 69
--- 24,30 ----
(define_insn_reservation "r4k_imul" 10
(and (eq_attr "cpu" "r4000")
! (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*10")
(define_insn_reservation "r4k_idiv" 69
Index: config/mips/4100.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/4100.md,v
retrieving revision 1.1
diff -c -3 -r1.1 4100.md
*** config/mips/4100.md 12 Jul 2004 05:21:29 -0000 1.1
--- config/mips/4100.md 11 May 2005 11:44:07 -0000
***************
*** 29,41 ****
(define_insn_reservation "r4100_imul_si" 1
(and (eq_attr "cpu" "r4100,r4120")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"imuldiv")
(define_insn_reservation "r4100_imul_di" 4
(and (eq_attr "cpu" "r4100,r4120")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"imuldiv*4")
--- 29,41 ----
(define_insn_reservation "r4100_imul_si" 1
(and (eq_attr "cpu" "r4100,r4120")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv")
(define_insn_reservation "r4100_imul_di" 4
(and (eq_attr "cpu" "r4100,r4120")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*4")
Index: config/mips/4130.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/4130.md,v
retrieving revision 1.1
diff -c -3 -r1.1 4130.md
*** config/mips/4130.md 6 May 2004 15:27:19 -0000 1.1
--- config/mips/4130.md 11 May 2005 11:44:07 -0000
***************
*** 55,61 ****
(cond [(eq_attr "type" "load,store")
(const_string "mem")
! (eq_attr "type" "mfhilo,mthilo,imul,imadd,idiv")
(const_string "mul")]
(const_string "alu")))
--- 55,61 ----
(cond [(eq_attr "type" "load,store")
(const_string "mem")
! (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
(const_string "mul")]
(const_string "alu")))
***************
*** 95,101 ****
;; use "mtlo; macc" instead of "mult; mflo".
(define_insn_reservation "vr4130_mulsi" 4
(and (eq_attr "cpu" "r4130")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr4130_muldiv + (vr4130_mulpre * 2)")
--- 95,101 ----
;; use "mtlo; macc" instead of "mult; mflo".
(define_insn_reservation "vr4130_mulsi" 4
(and (eq_attr "cpu" "r4130")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr4130_muldiv + (vr4130_mulpre * 2)")
***************
*** 103,109 ****
;; after 3 cycles.
(define_insn_reservation "vr4130_muldi" 6
(and (eq_attr "cpu" "r4130")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"(vr4130_muldiv * 3) + (vr4130_mulpre * 4)")
--- 103,109 ----
;; after 3 cycles.
(define_insn_reservation "vr4130_muldi" 6
(and (eq_attr "cpu" "r4130")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"(vr4130_muldiv * 3) + (vr4130_mulpre * 4)")
Index: config/mips/4300.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/4300.md,v
retrieving revision 1.2
diff -c -3 -r1.2 4300.md
*** config/mips/4300.md 18 Aug 2004 23:45:30 -0000 1.2
--- config/mips/4300.md 11 May 2005 11:44:07 -0000
***************
*** 29,41 ****
(define_insn_reservation "r4300_imul_si" 5
(and (eq_attr "cpu" "r4300")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r4300_imul_di" 8
(and (eq_attr "cpu" "r4300")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"imuldiv*8")
--- 29,41 ----
(define_insn_reservation "r4300_imul_si" 5
(and (eq_attr "cpu" "r4300")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r4300_imul_di" 8
(and (eq_attr "cpu" "r4300")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*8")
Index: config/mips/4600.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/4600.md,v
retrieving revision 1.2
diff -c -3 -r1.2 4600.md
*** config/mips/4600.md 18 Aug 2004 23:45:30 -0000 1.2
--- config/mips/4600.md 11 May 2005 11:44:07 -0000
***************
*** 27,33 ****
(define_insn_reservation "r4600_imul" 10
(and (eq_attr "cpu" "r4600")
! (eq_attr "type" "imul,imadd"))
"imuldiv*10")
(define_insn_reservation "r4600_idiv" 42
--- 27,33 ----
(define_insn_reservation "r4600_imul" 10
(and (eq_attr "cpu" "r4600")
! (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*10")
(define_insn_reservation "r4600_idiv" 42
***************
*** 38,44 ****
(define_insn_reservation "r4650_imul" 4
(and (eq_attr "cpu" "r4650")
! (eq_attr "type" "imul,imadd"))
"imuldiv*4")
(define_insn_reservation "r4650_idiv" 36
--- 38,44 ----
(define_insn_reservation "r4650_imul" 4
(and (eq_attr "cpu" "r4650")
! (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*4")
(define_insn_reservation "r4650_idiv" 36
Index: config/mips/5000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/5000.md,v
retrieving revision 1.2
diff -c -3 -r1.2 5000.md
*** config/mips/5000.md 18 Aug 2004 23:45:30 -0000 1.2
--- config/mips/5000.md 11 May 2005 11:44:07 -0000
***************
*** 29,41 ****
(define_insn_reservation "r5k_imul_si" 5
(and (eq_attr "cpu" "r5000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r5k_imul_di" 9
(and (eq_attr "cpu" "r5000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"imuldiv*9")
--- 29,41 ----
(define_insn_reservation "r5k_imul_si" 5
(and (eq_attr "cpu" "r5000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r5k_imul_di" 9
(and (eq_attr "cpu" "r5000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*9")
Index: config/mips/5400.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/5400.md,v
retrieving revision 1.7
diff -c -3 -r1.7 5400.md
*** config/mips/5400.md 18 Aug 2004 23:45:30 -0000 1.7
--- config/mips/5400.md 11 May 2005 11:44:07 -0000
***************
*** 65,83 ****
(define_insn_reservation "ir_vr54_imul_si" 3
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_di" 4
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imadd_si" 3
(and (eq_attr "cpu" "r5400")
! (eq_attr "type" "imul"))
"vr54_mac")
(define_insn_reservation "ir_vr54_idiv_si" 42
--- 65,83 ----
(define_insn_reservation "ir_vr54_imul_si" 3
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_di" 4
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imadd_si" 3
(and (eq_attr "cpu" "r5400")
! (eq_attr "type" "imul,imul3"))
"vr54_mac")
(define_insn_reservation "ir_vr54_idiv_si" 42
Index: config/mips/5500.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/5500.md,v
retrieving revision 1.8
diff -c -3 -r1.8 5500.md
*** config/mips/5500.md 18 Aug 2004 23:45:30 -0000 1.8
--- config/mips/5500.md 11 May 2005 11:44:07 -0000
***************
*** 78,84 ****
;; latency of {mul,mult}->{mfhi,mflo}.
(define_insn_reservation "ir_vr55_imul_si" 5
(and (eq_attr "cpu" "r5500")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "SI")))
"vr55_mac")
--- 78,84 ----
;; latency of {mul,mult}->{mfhi,mflo}.
(define_insn_reservation "ir_vr55_imul_si" 5
(and (eq_attr "cpu" "r5500")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr55_mac")
***************
*** 91,97 ****
;; between it and the dmult.
(define_insn_reservation "ir_vr55_imul_di" 9
(and (eq_attr "cpu" "r5500")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"vr55_mac*4")
--- 91,97 ----
;; between it and the dmult.
(define_insn_reservation "ir_vr55_imul_di" 9
(and (eq_attr "cpu" "r5500")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"vr55_mac*4")
Index: config/mips/7000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/7000.md,v
retrieving revision 1.8
diff -c -3 -r1.8 7000.md
*** config/mips/7000.md 18 Aug 2004 23:45:30 -0000 1.8
--- config/mips/7000.md 11 May 2005 11:44:07 -0000
***************
*** 111,117 ****
(define_insn_reservation "rm7_impy_si_mult" 5
(and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul,imadd")
(and (eq_attr "mode" "SI")
(match_operand 0 "hilo_operand"))))
"rm7_impydiv+(rm7_impydiv_iter*3)")
--- 111,117 ----
(define_insn_reservation "rm7_impy_si_mult" 5
(and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul,imul3,imadd")
(and (eq_attr "mode" "SI")
(match_operand 0 "hilo_operand"))))
"rm7_impydiv+(rm7_impydiv_iter*3)")
***************
*** 119,131 ****
;; There are an additional 2 stall cycles.
(define_insn_reservation "rm7_impy_si_mul" 2
(and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul,imadd")
(and (eq_attr "mode" "SI")
(not (match_operand 0 "hilo_operand")))))
"rm7_impydiv")
(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*8)")
--- 119,131 ----
;; There are an additional 2 stall cycles.
(define_insn_reservation "rm7_impy_si_mul" 2
(and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul,imul3,imadd")
(and (eq_attr "mode" "SI")
(not (match_operand 0 "hilo_operand")))))
"rm7_impydiv")
(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*8)")
Index: config/mips/9000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/9000.md,v
retrieving revision 1.6
diff -c -3 -r1.6 9000.md
*** config/mips/9000.md 18 Aug 2004 23:45:30 -0000 1.6
--- config/mips/9000.md 11 May 2005 11:44:07 -0000
***************
*** 64,76 ****
;; This applies to both 'mul' and 'mult'.
(define_insn_reservation "rm9k_mulsi" 3
(and (eq_attr "cpu" "r9000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "!DI")))
"rm9k_f_int")
(define_insn_reservation "rm9k_muldi" 7
(and (eq_attr "cpu" "r9000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"rm9k_f_int + rm9k_imul * 7")
--- 64,76 ----
;; This applies to both 'mul' and 'mult'.
(define_insn_reservation "rm9k_mulsi" 3
(and (eq_attr "cpu" "r9000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "!DI")))
"rm9k_f_int")
(define_insn_reservation "rm9k_muldi" 7
(and (eq_attr "cpu" "r9000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"rm9k_f_int + rm9k_imul * 7")
Index: config/mips/generic.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/generic.md,v
retrieving revision 1.3
diff -c -3 -r1.3 generic.md
*** config/mips/generic.md 3 Sep 2004 20:12:27 -0000 1.3
--- config/mips/generic.md 11 May 2005 11:44:07 -0000
***************
*** 48,54 ****
"imuldiv*3")
(define_insn_reservation "generic_imul" 17
! (eq_attr "type" "imul,imadd")
"imuldiv*17")
(define_insn_reservation "generic_idiv" 38
--- 48,54 ----
"imuldiv*3")
(define_insn_reservation "generic_imul" 17
! (eq_attr "type" "imul,imul3,imadd")
"imuldiv*17")
(define_insn_reservation "generic_idiv" 38
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.md,v
retrieving revision 1.317
diff -c -3 -r1.317 mips.md
*** config/mips/mips.md 9 May 2005 11:43:50 -0000 1.317
--- config/mips/mips.md 11 May 2005 11:44:10 -0000
***************
*** 126,132 ****
;; slt set less than instructions
;; clz the clz and clo instructions
;; trap trap if instructions
! ;; imul integer multiply
;; imadd integer multiply-add
;; idiv integer divide
;; fmove floating point register move
--- 126,133 ----
;; slt set less than instructions
;; clz the clz and clo instructions
;; trap trap if instructions
! ;; imul integer multiply 2 operands
! ;; imul3 integer multiply 3 operands
;; imadd integer multiply-add
;; idiv integer divide
;; fmove floating point register move
***************
*** 148,154 ****
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
! "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
--- 149,155 ----
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
! "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
***************
*** 253,259 ****
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
! (and (eq_attr "type" "imul")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
--- 254,260 ----
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
! (and (eq_attr "type" "imul,imul3")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
***************
*** 286,292 ****
(const_string "delay")
;; The r4000 multiplication patterns include an mflo instruction.
! (and (eq_attr "type" "imul")
(ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
(const_string "hilo")
--- 287,293 ----
(const_string "delay")
;; The r4000 multiplication patterns include an mflo instruction.
! (and (eq_attr "type" "imul,imul3")
(ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
(const_string "hilo")
***************
*** 317,323 ****
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
! (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
--- 318,324 ----
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
! (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
***************
*** 967,973 ****
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}
! [(set_attr "type" "imul")
(set_attr "mode" "SI")])
(define_insn "muldi3_mult3"
--- 968,974 ----
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}
! [(set_attr "type" "imul3,imul")
(set_attr "mode" "SI")])
(define_insn "muldi3_mult3"
***************
*** 978,984 ****
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && GENERATE_MULT3_DI"
"dmult\t%0,%1,%2"
! [(set_attr "type" "imul")
(set_attr "mode" "DI")])
;; If a register gets allocated to LO, and we spill to memory, the reload
--- 979,985 ----
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && GENERATE_MULT3_DI"
"dmult\t%0,%1,%2"
! [(set_attr "type" "imul3")
(set_attr "mode" "DI")])
;; If a register gets allocated to LO, and we spill to memory, the reload
***************
*** 1025,1031 ****
(clobber (match_scratch:GPR 4 "=l"))]
"TARGET_FIX_R4000"
"<d>mult\t%1,%2\;mflo\t%0"
! [(set_attr "type" "imul")
(set_attr "mode" "<MODE>")
(set_attr "length" "8")])
--- 1026,1032 ----
(clobber (match_scratch:GPR 4 "=l"))]
"TARGET_FIX_R4000"
"<d>mult\t%1,%2\;mflo\t%0"
! [(set_attr "type" "imul3")
(set_attr "mode" "<MODE>")
(set_attr "length" "8")])
***************
*** 1400,1406 ****
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
! [(set_attr "type" "imul")
(set_attr "mode" "SI")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
--- 1401,1407 ----
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
! [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
***************
*** 1443,1449 ****
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
"mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
! [(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "12")])
--- 1444,1450 ----
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
"mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
! [(set_attr "type" "imul3")
(set_attr "mode" "SI")
(set_attr "length" "12")])
***************
*** 1490,1496 ****
(ior:DI (match_dup 0)
(match_dup 5)))]
""
! [(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "24")])
--- 1491,1497 ----
(ior:DI (match_dup 0)
(match_dup 5)))]
""
! [(set_attr "type" "imul3")
(set_attr "mode" "SI")
(set_attr "length" "24")])
***************
*** 1586,1592 ****
"@
mult<u>\t%1,%2
mulhi<u>\t%0,%1,%2"
! [(set_attr "type" "imul")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
--- 1587,1593 ----
"@
mult<u>\t%1,%2
mulhi<u>\t%0,%1,%2"
! [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
***************
*** 1604,1610 ****
"@
mulshi<u>\t%.,%1,%2
mulshi<u>\t%0,%1,%2"
! [(set_attr "type" "imul")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
--- 1605,1611 ----
"@
mulshi<u>\t%.,%1,%2
mulshi<u>\t%0,%1,%2"
! [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
Index: config/mips/sb1.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/sb1.md,v
retrieving revision 1.9
diff -c -3 -r1.9 sb1.md
*** config/mips/sb1.md 3 Sep 2004 20:12:29 -0000 1.9
--- config/mips/sb1.md 11 May 2005 11:44:10 -0000
***************
*** 296,302 ****
(define_insn_reservation "ir_sb1_mulsi" 3
(and (eq_attr "cpu" "sb1")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"sb1_ex1+sb1_mul")
--- 296,302 ----
(define_insn_reservation "ir_sb1_mulsi" 3
(and (eq_attr "cpu" "sb1")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"sb1_ex1+sb1_mul")
***************
*** 305,311 ****
(define_insn_reservation "ir_sb1_muldi" 4
(and (eq_attr "cpu" "sb1")
! (and (eq_attr "type" "imul")
(eq_attr "mode" "DI")))
"sb1_ex1+sb1_mul, sb1_mul")
--- 305,311 ----
(define_insn_reservation "ir_sb1_muldi" 4
(and (eq_attr "cpu" "sb1")
! (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"sb1_ex1+sb1_mul, sb1_mul")
Index: config/mips/sr71k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/sr71k.md,v
retrieving revision 1.10
diff -c -3 -r1.10 sr71k.md
*** config/mips/sr71k.md 18 Aug 2004 23:45:32 -0000 1.10
--- config/mips/sr71k.md 11 May 2005 11:44:10 -0000
***************
*** 209,222 ****
(define_insn_reservation "ir_sr70_imul_si"
4
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"ri_alux,ipu_alux,ipu_macc_iter")
(define_insn_reservation "ir_sr70_imul_di"
6
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"ri_alux,ipu_alux,(ipu_macc_iter*3)")
--- 209,222 ----
(define_insn_reservation "ir_sr70_imul_si"
4
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"ri_alux,ipu_alux,ipu_macc_iter")
(define_insn_reservation "ir_sr70_imul_di"
6
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"ri_alux,ipu_alux,(ipu_macc_iter*3)")