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Re: [s390] macros patch 9/11


Hi,

Here is the nineth patch. It combines almost all sf/df patterns.


2005-05-09  Adrian Straetling  <straetling@de.ibm.com>

	* config/s390/s390.md: ("FPR") New mode macro.
	("de", "dee"): New mode attributes.
	("cmpdf", "cmpsf"): Merge.
	("*cmpdf_ccs_0", "*cmpsf_ccs_0"): Merge.
	("*cmpdf_ccs_0_ibm", "*cmpdf_ccs_0_ibm"): Merge.
	("*cmpdf_ccs", "*cmpsf_ccs"): Merge.
	("*cmpdf_ccs_ibm", "*cmpsf_ccs_ibm"): Merge.
	("floatdidf2", "floatdisf2"): Merge.
	("adddf3", "addsf3"): Merge.
	("*adddf3", "*addsf3"): Merge.
	("*adddf3_cc", "*addsf3_cc"): Merge.
	("*adddf3_cconly", "*addsf3_cconly"): Merge.
	("*adddf3_ibm", "*addsf3_ibm"): Merge.
	("subdf3", "subsf3"): Merge.
	("*subdf3", "*subsf3"): Merge.
	("*subdf3_cc", "*subsf3_cc"): Merge.
	("*subdf3_cconly", "*subsf3_cconly"): Merge.
	("*subdf3_ibm", "*subsf3_ibm"): Merge.
	("muldf3", "mulsf3"): Merge.
	("*muldf3", "*mulsf3" "): Merge.
	("*muldf3_ibm", "*mulsf3_ibm"): Merge.
	("*fmadddf", "*fmaddsf"): Merge.
	("*fmsubdf", "*fmsubsf"): Merge.
	("divdf3", "divsf3"): Merge.
	("*divdf3", "*divsf3"): Merge.
	("*divdf3_ibm", "*divsf3_ibm"): Merge.
	("negdf2", "negsf2"):  Merge.
	("*negdf2_cc", "*negsf2_cc"): Merge.
	("*negdf2_cconly", "*negsf2_cconly"): Merge.
	("*negdf2", "*negsf2"):  Merge.
	("*negdf2_ibm", "*negsf2_ibm"):  Merge.
        ("absdf2",  "abssf2"):  Merge.
        ("*absdf2_cc", "*abssf2_cc"):  Merge.
        ("*absdf2_cconly", "*abssf2_cconly"):  Merge.
        ("*absdf2", "*abssf2"):  Merge.
        ("*absdf2_ibm", "*abssf2_ibm"):  Merge.
        ("*negabsdf2_cc", "*negabssf2_cc"):  Merge.
        ("*negabsdf2_cconly", "*negabssf2_cconly"): Merge.
        ("*negabsdf2", "*negabssf2"):  Merge.
        ("sqrtdf2", "sqrtsf2"):  Merge.


Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig	2005-05-04 18:15:31.271486453 +0200
--- gcc/config/s390/s390.md	2005-05-04 18:15:34.851486453 +0200
***************
*** 235,240 ****
--- 235,244 ----
  
  ;; Macros
  
+ ;; This mode macro allows DF and SF patterns to be generated from the
+ ;; same template.
+ (define_mode_macro FPR     [DF SF])
+ 
  ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
  ;; from the same template.
  (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
***************
*** 264,269 ****
--- 268,281 ----
  (define_code_macro SHIFT [ashift lshiftrt])
  
  
+ ;; in FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
+ ;; and "ltebr" in SFmode.
+ (define_mode_attr de [(DF "d") (SF "e")])
+ 
+ ;; in FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
+ ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern. 
+ (define_mode_attr dee [(DF "d") (SF "ee")])
+ 
  ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 
  ;; 'ashift' and "srdl" in 'lshiftrt'.
  (define_code_attr lr [(ashift "l") (lshiftrt "r")])
***************
*** 311,331 ****
    DONE;
  })
  
! (define_expand "cmpdf"
!   [(set (reg:CC 33)
!         (compare:CC (match_operand:DF 0 "register_operand" "")
!                     (match_operand:DF 1 "general_operand" "")))]
!   "TARGET_HARD_FLOAT"
! {
!   s390_compare_op0 = operands[0];
!   s390_compare_op1 = operands[1];
!   DONE;
! })
! 
! (define_expand "cmpsf"
    [(set (reg:CC 33)
!         (compare:CC (match_operand:SF 0 "register_operand" "")
!                     (match_operand:SF 1 "general_operand" "")))]
    "TARGET_HARD_FLOAT"
  {
    s390_compare_op0 = operands[0];
--- 323,332 ----
    DONE;
  })
  
! (define_expand "cmp<mode>"
    [(set (reg:CC 33)
!         (compare:CC (match_operand:FPR 0 "register_operand" "")
!                     (match_operand:FPR 1 "general_operand" "")))]
    "TARGET_HARD_FLOAT"
  {
    s390_compare_op0 = operands[0];
***************
*** 692,781 ****
  })
  
  
! ; DF instructions
! 
! (define_insn "*cmpdf_ccs_0"
!   [(set (reg 33)
!         (compare (match_operand:DF 0 "register_operand" "f")
!                  (match_operand:DF 1 "const0_operand" "")))]
!   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "ltdbr\t%0,%0"
!    [(set_attr "op_type" "RRE")
!     (set_attr "type"  "fsimpdf")])
! 
! (define_insn "*cmpdf_ccs_0_ibm"
!   [(set (reg 33)
!         (compare (match_operand:DF 0 "register_operand" "f")
!                  (match_operand:DF 1 "const0_operand" "")))]
!   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "ltdr\t%0,%0"
!    [(set_attr "op_type" "RR")
!     (set_attr "type"  "fsimpdf")])
! 
! (define_insn "*cmpdf_ccs"
!   [(set (reg 33)
!         (compare (match_operand:DF 0 "register_operand" "f,f")
!                  (match_operand:DF 1 "general_operand" "f,R")))]
!   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    cdbr\t%0,%1
!    cdb\t%0,%1"
!    [(set_attr "op_type" "RRE,RXE")
!     (set_attr "type"  "fsimpdf")])
! 
! (define_insn "*cmpdf_ccs_ibm"
!   [(set (reg 33)
!         (compare (match_operand:DF 0 "register_operand" "f,f")
!                  (match_operand:DF 1 "general_operand" "f,R")))]
!   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "@
!    cdr\t%0,%1
!    cd\t%0,%1"
!    [(set_attr "op_type" "RR,RX")
!     (set_attr "type"  "fsimpdf")])
! 
! 
! ; SF instructions
  
! (define_insn "*cmpsf_ccs_0"
    [(set (reg 33)
!         (compare (match_operand:SF 0 "register_operand" "f")
!                  (match_operand:SF 1 "const0_operand" "")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "ltebr\t%0,%0"
     [(set_attr "op_type" "RRE")
!     (set_attr "type"  "fsimpsf")])
  
! (define_insn "*cmpsf_ccs_0_ibm"
    [(set (reg 33)
!         (compare (match_operand:SF 0 "register_operand" "f")
!                  (match_operand:SF 1 "const0_operand" "")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lter\t%0,%0"
     [(set_attr "op_type" "RR")
!     (set_attr "type"  "fsimpsf")])
  
! (define_insn "*cmpsf_ccs"
    [(set (reg 33)
!         (compare (match_operand:SF 0 "register_operand" "f,f")
!                  (match_operand:SF 1 "general_operand" "f,R")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    cebr\t%0,%1
!    ceb\t%0,%1"
     [(set_attr "op_type" "RRE,RXE")
!     (set_attr "type"  "fsimpsf")])
  
! (define_insn "*cmpsf_ccs"
    [(set (reg 33)
!         (compare (match_operand:SF 0 "register_operand" "f,f")
!                  (match_operand:SF 1 "general_operand" "f,R")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    cer\t%0,%1
!    ce\t%0,%1"
     [(set_attr "op_type" "RR,RX")
!     (set_attr "type"  "fsimpsf")])
  
  
  ;;
--- 693,739 ----
  })
  
  
! ; (DF|SF) instructions
  
! (define_insn "*cmp<mode>_ccs_0"
    [(set (reg 33)
!         (compare (match_operand:FPR 0 "register_operand" "f")
!                  (match_operand:FPR 1 "const0_operand" "")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lt<de>br\t%0,%0"
     [(set_attr "op_type" "RRE")
!     (set_attr "type"  "fsimp<mode>")])
  
! (define_insn "*cmp<mode>_ccs_0_ibm"
    [(set (reg 33)
!         (compare (match_operand:FPR 0 "register_operand" "f")
!                  (match_operand:FPR 1 "const0_operand" "")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lt<de>r\t%0,%0"
     [(set_attr "op_type" "RR")
!     (set_attr "type"  "fsimp<mode>")])
  
! (define_insn "*cmp<mode>_ccs"
    [(set (reg 33)
!         (compare (match_operand:FPR 0 "register_operand" "f,f")
!                  (match_operand:FPR 1 "general_operand" "f,R")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    c<de>br\t%0,%1
!    c<de>b\t%0,%1"
     [(set_attr "op_type" "RRE,RXE")
!     (set_attr "type"  "fsimp<mode>")])
  
! (define_insn "*cmp<mode>_ccs_ibm"
    [(set (reg 33)
!         (compare (match_operand:FPR 0 "register_operand" "f,f")
!                  (match_operand:FPR 1 "general_operand" "f,R")))]
    "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    c<de>r\t%0,%1
!    c<de>\t%0,%1"
     [(set_attr "op_type" "RR,RX")
!     (set_attr "type"  "fsimp<mode>")])
  
  
  ;;
***************
*** 2954,2979 ****
     (set_attr "type"    "ftoi")])
  
  ;
! ; floatdidf2 instruction pattern(s).
  ;
  
! (define_insn "floatdidf2"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (float:DF (match_operand:DI 1 "register_operand" "d")))]
    "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "cdgbr\t%0,%1"
!   [(set_attr "op_type" "RRE")
!    (set_attr "type"    "itof" )])
! 
! ;
! ; floatdisf2 instruction pattern(s).
! ;
! 
! (define_insn "floatdisf2"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (float:SF (match_operand:DI 1 "register_operand" "d")))]
!   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "cegbr\t%0,%1"
    [(set_attr "op_type" "RRE")
     (set_attr "type"    "itof" )])
  
--- 2912,2925 ----
     (set_attr "type"    "ftoi")])
  
  ;
! ; floatdi(df|sf)2 instruction pattern(s).
  ;
  
! (define_insn "floatdi<mode>2"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (float:FPR (match_operand:DI 1 "register_operand" "d")))]
    "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "c<de>gbr\t%0,%1"
    [(set_attr "op_type" "RRE")
     (set_attr "type"    "itof" )])
  
***************
*** 3514,3645 ****
    [(set_attr "op_type"  "RR,RI,RX,RXY")])
  
  ;
! ; adddf3 instruction pattern(s).
! ;
! 
! (define_expand "adddf3"
!   [(parallel
!     [(set (match_operand:DF 0 "register_operand" "=f,f")
!           (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                    (match_operand:DF 2 "general_operand" "f,R")))
!      (clobber (reg:CC 33))])]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*adddf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:DF 2 "general_operand" "f,R")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    adbr\t%0,%2
!    adb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*adddf3_cc"
!   [(set (reg 33)
! 	(compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! 			  (match_operand:DF 2 "general_operand" "f,R"))
! 		 (match_operand:DF 3 "const0_operand" "")))
!    (set (match_operand:DF 0 "register_operand" "=f,f")
! 	(plus:DF (match_dup 1) (match_dup 2)))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    adbr\t%0,%2
!    adb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*adddf3_cconly"
!   [(set (reg 33)
! 	(compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! 			  (match_operand:DF 2 "general_operand" "f,R"))
! 		 (match_operand:DF 3 "const0_operand" "")))
!    (clobber (match_scratch:DF 0 "=f,f"))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!   adbr\t%0,%2
!   adb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*adddf3_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:DF 2 "general_operand" "f,R")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "@
!    adr\t%0,%2
!    ad\t%0,%2"
!   [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimpdf")])
! 
! ;
! ; addsf3 instruction pattern(s).
  ;
  
! (define_expand "addsf3"
    [(parallel
!     [(set (match_operand:SF 0 "register_operand" "=f,f")
!           (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                    (match_operand:SF 2 "general_operand" "f,R")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*addsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:SF 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    aebr\t%0,%2
!    aeb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
  
! (define_insn "*addsf3_cc"
    [(set (reg 33)
! 	(compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! 			  (match_operand:SF 2 "general_operand" "f,R"))
! 		 (match_operand:SF 3 "const0_operand" "")))
!    (set (match_operand:SF 0 "register_operand" "=f,f")
! 	(plus:SF (match_dup 1) (match_dup 2)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    aebr\t%0,%2
!    aeb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
  
! (define_insn "*addsf3_cconly"
    [(set (reg 33)
! 	(compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! 			  (match_operand:SF 2 "general_operand" "f,R"))
! 		 (match_operand:SF 3 "const0_operand" "")))
!    (clobber (match_scratch:SF 0 "=f,f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    aebr\t%0,%2
!    aeb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
  
! (define_insn "*addsf3_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:SF 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    aer\t%0,%2
!    ae\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimpsf")])
  
  
  ;;
--- 3460,3527 ----
    [(set_attr "op_type"  "RR,RI,RX,RXY")])
  
  ;
! ; add(df|sf)3 instruction pattern(s).
  ;
  
! (define_expand "add<mode>3"
    [(parallel
!     [(set (match_operand:FPR 0 "register_operand" "=f,f")
!           (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                     (match_operand:FPR 2 "general_operand" "f,R")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*add<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                   (match_operand:FPR 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    a<de>br\t%0,%2
!    a<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*add<mode>3_cc"
    [(set (reg 33)
! 	(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! 			   (match_operand:FPR 2 "general_operand" "f,R"))
! 		 (match_operand:FPR 3 "const0_operand" "")))
!    (set (match_operand:FPR 0 "register_operand" "=f,f")
! 	(plus:FPR (match_dup 1) (match_dup 2)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    a<de>br\t%0,%2
!    a<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*add<mode>3_cconly"
    [(set (reg 33)
! 	(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
! 			   (match_operand:FPR 2 "general_operand" "f,R"))
! 		 (match_operand:FPR 3 "const0_operand" "")))
!    (clobber (match_scratch:FPR 0 "=f,f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    a<de>br\t%0,%2
!    a<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*add<mode>3_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                   (match_operand:FPR 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    a<de>r\t%0,%2
!    a<de>\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimp<mode>")])
  
  
  ;;
***************
*** 3982,4113 ****
  
  
  ;
! ; subdf3 instruction pattern(s).
  ;
  
! (define_expand "subdf3"
    [(parallel
!     [(set (match_operand:DF 0 "register_operand" "=f,f")
!           (minus:DF (match_operand:DF 1 "register_operand" "0,0")
!                     (match_operand:DF 2 "general_operand" "f,R")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*subdf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
!                   (match_operand:DF 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    sdbr\t%0,%2
!    sdb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
  
! (define_insn "*subdf3_cc"
    [(set (reg 33)
! 	(compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
! 			   (match_operand:DF 2 "general_operand" "f,R"))
! 		 (match_operand:DF 3 "const0_operand" "")))
!    (set (match_operand:DF 0 "register_operand" "=f,f")
! 	(minus:DF (match_dup 1) (match_dup 2)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    sdbr\t%0,%2
!    sdb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
  
! (define_insn "*subdf3_cconly"
    [(set (reg 33)
! 	(compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
! 			   (match_operand:DF 2 "general_operand" "f,R"))
! 		 (match_operand:DF 3 "const0_operand" "")))
!    (clobber (match_scratch:DF 0 "=f,f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    sdbr\t%0,%2
!    sdb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpdf")])
  
! (define_insn "*subdf3_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (minus:DF (match_operand:DF 1 "register_operand" "0,0")
!                   (match_operand:DF 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    sdr\t%0,%2
!    sd\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimpdf")])
! 
! ;
! ; subsf3 instruction pattern(s).
! ;
! 
! (define_expand "subsf3"
!   [(parallel
!     [(set (match_operand:SF 0 "register_operand" "=f,f")
!           (minus:SF (match_operand:SF 1 "register_operand" "0,0")
!                     (match_operand:SF 2 "general_operand" "f,R")))
!      (clobber (reg:CC 33))])]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*subsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
!                   (match_operand:SF 2 "general_operand" "f,R")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    sebr\t%0,%2
!    seb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
! 
! (define_insn "*subsf3_cc"
!   [(set (reg 33)
! 	(compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
! 			   (match_operand:SF 2 "general_operand" "f,R"))
! 		 (match_operand:SF 3 "const0_operand" "")))
!    (set (match_operand:SF 0 "register_operand" "=f,f")
! 	(minus:SF (match_dup 1) (match_dup 2)))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    sebr\t%0,%2
!    seb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
! 
! (define_insn "*subsf3_cconly"
!   [(set (reg 33)
! 	(compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
! 			   (match_operand:SF 2 "general_operand" "f,R"))
! 		 (match_operand:SF 3 "const0_operand" "")))
!    (clobber (match_scratch:SF 0 "=f,f"))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    sebr\t%0,%2
!    seb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimpsf")])
! 
! (define_insn "*subsf3_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (minus:SF (match_operand:SF 1 "register_operand" "0,0")
!                   (match_operand:SF 2 "general_operand" "f,R")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "@
!    ser\t%0,%2
!    se\t%0,%2"
!   [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimpsf")])
  
  
  ;;
--- 3864,3931 ----
  
  
  ;
! ; sub(df|sf)3 instruction pattern(s).
  ;
  
! (define_expand "sub<mode>3"
    [(parallel
!     [(set (match_operand:FPR 0 "register_operand" "=f,f")
!           (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                      (match_operand:FPR 2 "general_operand" "f,R")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*sub<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                    (match_operand:FPR 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    s<de>br\t%0,%2
!    s<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*sub<mode>3_cc"
    [(set (reg 33)
! 	(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
! 			    (match_operand:FPR 2 "general_operand" "f,R"))
! 		 (match_operand:FPR 3 "const0_operand" "")))
!    (set (match_operand:FPR 0 "register_operand" "=f,f")
! 	(minus:FPR (match_dup 1) (match_dup 2)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    s<de>br\t%0,%2
!    s<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*sub<mode>3_cconly"
    [(set (reg 33)
! 	(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
! 			    (match_operand:FPR 2 "general_operand" "f,R"))
! 		 (match_operand:FPR 3 "const0_operand" "")))
!    (clobber (match_scratch:FPR 0 "=f,f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    s<de>br\t%0,%2
!    s<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*sub<mode>3_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                    (match_operand:FPR 2 "general_operand" "f,R")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    s<de>r\t%0,%2
!    s<de>\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fsimp<mode>")])
  
  
  ;;
***************
*** 4320,4437 ****
     (set_attr "type"     "imulsi")])
  
  ;
! ; muldf3 instruction pattern(s).
  ;
  
! (define_expand "muldf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*muldf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    mdbr\t%0,%2
!    mdb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fmuldf")])
  
! (define_insn "*muldf3_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    mdr\t%0,%2
!    md\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"    "fmuldf")])
  
! (define_insn "*fmadddf"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
! 	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
! 			  (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
! 		 (match_operand:DF 3 "register_operand" "0,0")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
    "@
!    madbr\t%0,%1,%2
!    madb\t%0,%1,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type" "fmuldf")])
  
! (define_insn "*fmsubdf"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
! 	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
! 			   (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
! 		 (match_operand:DF 3 "register_operand" "0,0")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
    "@
!    msdbr\t%0,%1,%2
!    msdb\t%0,%1,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type" "fmuldf")])
! 
! ;
! ; mulsf3 instruction pattern(s).
! ;
! 
! (define_expand "mulsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*mulsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    meebr\t%0,%2
!    meeb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fmulsf")])
! 
! (define_insn "*mulsf3_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
!                  (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "@
!    mer\t%0,%2
!    me\t%0,%2"
!   [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fmulsf")])
! 
! (define_insn "*fmaddsf"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
! 	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
! 			  (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
! 		 (match_operand:SF 3 "register_operand" "0,0")))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
!   "@
!    maebr\t%0,%1,%2
!    maeb\t%0,%1,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type" "fmulsf")])
! 
! (define_insn "*fmsubsf"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
! 	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
! 			   (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
! 		  (match_operand:SF 3 "register_operand" "0,0")))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
!   "@
!    msebr\t%0,%1,%2
!    mseb\t%0,%1,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type" "fmulsf")])
  
  ;;
  ;;- Divide and modulo instructions.
--- 4138,4198 ----
     (set_attr "type"     "imulsi")])
  
  ;
! ; mul(df|sf)3 instruction pattern(s).
  ;
  
! (define_expand "mul<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                   (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*mul<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                   (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    m<dee>br\t%0,%2
!    m<dee>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fmul<mode>")])
  
! (define_insn "*mul<mode>3_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
!                   (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    m<de>r\t%0,%2
!    m<de>\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fmul<mode>")])
  
! (define_insn "*fmadd<mode>"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
! 	(plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
! 			   (match_operand:FPR 2 "nonimmediate_operand"  "f,R"))
! 		 (match_operand:FPR 3 "register_operand" "0,0")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
    "@
!    ma<de>br\t%0,%1,%2
!    ma<de>b\t%0,%1,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fmul<mode>")])
  
! (define_insn "*fmsub<mode>"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
! 	(minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
! 			    (match_operand:FPR 2 "nonimmediate_operand"  "f,R"))
! 		 (match_operand:FPR 3 "register_operand" "0,0")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
    "@
!    ms<de>br\t%0,%1,%2
!    ms<de>b\t%0,%1,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fmul<mode>")])
  
  ;;
  ;;- Divide and modulo instructions.
***************
*** 4870,4939 ****
  })
  
  ;
! ; divdf3 instruction pattern(s).
  ;
  
! (define_expand "divdf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (div:DF (match_operand:DF 1 "register_operand" "0,0")
!                 (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*divdf3"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (div:DF (match_operand:DF 1 "register_operand" "0,0")
!                 (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    ddbr\t%0,%2
!    ddb\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fdivdf")])
  
! (define_insn "*divdf3_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
!         (div:DF (match_operand:DF 1 "register_operand" "0,0")
!                 (match_operand:DF 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    ddr\t%0,%2
!    dd\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fdivdf")])
! 
! ;
! ; divsf3 instruction pattern(s).
! ;
! 
! (define_expand "divsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (div:SF (match_operand:SF 1 "register_operand" "0,0")
!                 (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*divsf3"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (div:SF (match_operand:SF 1 "register_operand" "0,0")
!                 (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "@
!    debr\t%0,%2
!    deb\t%0,%2"
!   [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fdivsf")])
! 
! (define_insn "*divsf3_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f,f")
!         (div:SF (match_operand:SF 1 "register_operand" "0,0")
!                 (match_operand:SF 2 "general_operand" "f,R")))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "@
!    der\t%0,%2
!    de\t%0,%2"
!   [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fdivsf")])
  
  
  ;;
--- 4631,4667 ----
  })
  
  ;
! ; div(df|sf)3 instruction pattern(s).
  ;
  
! (define_expand "div<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                  (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*div<mode>3"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                  (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    d<de>br\t%0,%2
!    d<de>b\t%0,%2"
    [(set_attr "op_type"  "RRE,RXE")
!    (set_attr "type"     "fdiv<mode>")])
  
! (define_insn "*div<mode>3_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
!         (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
!                  (match_operand:FPR 2 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
    "@
!    d<de>r\t%0,%2
!    d<de>\t%0,%2"
    [(set_attr "op_type"  "RR,RX")
!    (set_attr "type"     "fdiv<mode>")])
  
  
  ;;
***************
*** 5893,5998 ****
     operands[6] = gen_label_rtx ();")
  
  ;
! ; negdf2 instruction pattern(s).
! ;
! 
! (define_expand "negdf2"
!   [(parallel
!     [(set (match_operand:DF 0 "register_operand" "=f")
!           (neg:DF (match_operand:DF 1 "register_operand" "f")))
!      (clobber (reg:CC 33))])]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*negdf2_cc"
!   [(set (reg 33)
!         (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (set (match_operand:DF 0 "register_operand" "=f")
!         (neg:DF (match_dup 1)))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*negdf2_cconly"
!   [(set (reg 33)
!         (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (clobber (match_scratch:DF 0 "=f"))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*negdf2"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (neg:DF (match_operand:DF 1 "register_operand" "f")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*negdf2_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (neg:DF (match_operand:DF 1 "register_operand" "f")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lcdr\t%0,%1"
!   [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimpdf")])
! 
! ;
! ; negsf2 instruction pattern(s).
  ;
  
! (define_expand "negsf2"
    [(parallel
!     [(set (match_operand:SF 0 "register_operand" "=f")
!           (neg:SF (match_operand:SF 1 "register_operand" "f")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*negsf2_cc"
    [(set (reg 33)
!         (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (set (match_operand:SF 0 "register_operand" "=f")
!         (neg:SF (match_dup 1)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*negsf2_cconly"
    [(set (reg 33)
!         (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (clobber (match_scratch:SF 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*negsf2"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (neg:SF (match_operand:SF 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lcebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
  
! (define_insn "*negsf2_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (neg:SF (match_operand:SF 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lcer\t%0,%1"
    [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimpsf")])
  
  
  ;;
--- 5621,5675 ----
     operands[6] = gen_label_rtx ();")
  
  ;
! ; neg(df|sf)2 instruction pattern(s).
  ;
  
! (define_expand "neg<mode>2"
    [(parallel
!     [(set (match_operand:FPR 0 "register_operand" "=f")
!           (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*neg<mode>2_cc"
    [(set (reg 33)
!         (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (set (match_operand:FPR 0 "register_operand" "=f")
!         (neg:FPR (match_dup 1)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lc<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*neg<mode>2_cconly"
    [(set (reg 33)
!         (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (clobber (match_scratch:FPR 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lc<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*neg<mode>2"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lc<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*neg<mode>2_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lc<de>r\t%0,%1"
    [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimp<mode>")])
  
  
  ;;
***************
*** 6051,6156 ****
    [(set_attr "op_type"  "RR<E>")])
  
  ;
! ; absdf2 instruction pattern(s).
! ;
! 
! (define_expand "absdf2"
!   [(parallel
!     [(set (match_operand:DF 0 "register_operand" "=f")
!           (abs:DF (match_operand:DF 1 "register_operand" "f")))
!      (clobber (reg:CC 33))])]
!   "TARGET_HARD_FLOAT"
!   "")
! 
! (define_insn "*absdf2_cc"
!   [(set (reg 33)
!         (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (set (match_operand:DF 0 "register_operand" "=f")
!         (abs:DF (match_dup 1)))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*absdf2_cconly"
!   [(set (reg 33)
!         (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (clobber (match_scratch:DF 0 "=f"))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*absdf2"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (abs:DF (match_operand:DF 1 "register_operand" "f")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpdbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*absdf2_ibm"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (abs:DF (match_operand:DF 1 "register_operand" "f")))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lpdr\t%0,%1"
!   [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimpdf")])
! 
! ;
! ; abssf2 instruction pattern(s).
  ;
  
! (define_expand "abssf2"
    [(parallel
!     [(set (match_operand:SF 0 "register_operand" "=f")
!           (abs:SF (match_operand:SF 1 "register_operand" "f")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*abssf2_cc"
    [(set (reg 33)
!         (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (set (match_operand:SF 0 "register_operand" "=f")
!         (abs:SF (match_dup 1)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*abssf2_cconly"
    [(set (reg 33)
!         (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (clobber (match_scratch:SF 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*abssf2"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (abs:SF (match_operand:SF 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lpebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
  
! (define_insn "*abssf2_ibm"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (abs:SF (match_operand:SF 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lper\t%0,%1"
    [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimpsf")])
  
  ;;
  ;;- Negated absolute value instructions
--- 5728,5782 ----
    [(set_attr "op_type"  "RR<E>")])
  
  ;
! ; abs(df|sf)2 instruction pattern(s).
  ;
  
! (define_expand "abs<mode>2"
    [(parallel
!     [(set (match_operand:FPR 0 "register_operand" "=f")
!           (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
       (clobber (reg:CC 33))])]
    "TARGET_HARD_FLOAT"
    "")
  
! (define_insn "*abs<mode>2_cc"
    [(set (reg 33)
!         (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (set (match_operand:FPR 0 "register_operand" "=f")
!         (abs:FPR (match_dup 1)))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lp<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*abs<mode>2_cconly"
    [(set (reg 33)
!         (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (clobber (match_scratch:FPR 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lp<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*abs<mode>2"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lp<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
  
! (define_insn "*abs<mode>2_ibm"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
!   "lp<de>r\t%0,%1"
    [(set_attr "op_type"  "RR")
!    (set_attr "type"     "fsimp<mode>")])
  
  ;;
  ;;- Negated absolute value instructions
***************
*** 6212,6308 ****
  ; Floating point
  ;
  
! (define_insn "*negabsdf2_cc"
!   [(set (reg 33)
!         (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (set (match_operand:DF 0 "register_operand" "=f")
!         (neg:DF (abs:DF (match_dup 1))))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lndbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*negabsdf2_cconly"
!   [(set (reg 33)
!         (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
!                  (match_operand:DF 2 "const0_operand" "")))
!    (clobber (match_scratch:DF 0 "=f"))]
!   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lndbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
!   
! (define_insn "*negabsdf2"
!   [(set (match_operand:DF 0 "register_operand" "=f")
!         (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
!    (clobber (reg:CC 33))]
!   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lndbr\t%0,%1"
!   [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpdf")])
! 
! (define_insn "*negabssf2_cc"
    [(set (reg 33)
!         (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (set (match_operand:SF 0 "register_operand" "=f")
!         (neg:SF (abs:SF (match_dup 1))))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lnebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*negabssf2_cconly"
    [(set (reg 33)
!         (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
!                  (match_operand:SF 2 "const0_operand" "")))
!    (clobber (match_scratch:SF 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lnebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
    
! (define_insn "*negabssf2"
!   [(set (match_operand:SF 0 "register_operand" "=f")
!         (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "lnebr\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimpsf")])
  
  ;;
  ;;- Square root instructions.
  ;;
  
  ;
! ; sqrtdf2 instruction pattern(s).
  ;
  
! (define_insn "sqrtdf2"
!   [(set (match_operand:DF 0 "register_operand" "=f,f")
! 	(sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    sqdbr\t%0,%1
!    sqdb\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
!    (set_attr "type" "fsqrtdf")])
  
- ;
- ; sqrtsf2 instruction pattern(s).
- ;
- 
- (define_insn "sqrtsf2"
-   [(set (match_operand:SF 0 "register_operand" "=f,f")
- 	(sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
-   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-   "@
-    sqebr\t%0,%1
-    sqeb\t%0,%1"
-   [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type" "fsqrtsf")])
  
  ;;
  ;;- One complement instructions.
--- 5838,5891 ----
  ; Floating point
  ;
  
! (define_insn "*negabs<mode>2_cc"
    [(set (reg 33)
!         (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (set (match_operand:FPR 0 "register_operand" "=f")
!         (neg:FPR (abs:FPR (match_dup 1))))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "ln<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*negabs<mode>2_cconly"
    [(set (reg 33)
!         (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
!                  (match_operand:FPR 2 "const0_operand" "")))
!    (clobber (match_scratch:FPR 0 "=f"))]
    "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "ln<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
    
! (define_insn "*negabs<mode>2"
!   [(set (match_operand:FPR 0 "register_operand" "=f")
!         (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
     (clobber (reg:CC 33))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
!   "ln<de>br\t%0,%1"
    [(set_attr "op_type"  "RRE")
!    (set_attr "type"     "fsimp<mode>")])
  
  ;;
  ;;- Square root instructions.
  ;;
  
  ;
! ; sqrt(df|sf)2 instruction pattern(s).
  ;
  
! (define_insn "sqrt<mode>2"
!   [(set (match_operand:FPR 0 "register_operand" "=f,f")
! 	(sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
    "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
    "@
!    sq<de>br\t%0,%1
!    sq<de>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
!    (set_attr "type" "fsqrt<mode>")])
  
  
  ;;
  ;;- One complement instructions.


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