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Re: [s390] macros patch 5/11


Hi,

Here is the fifth patch dealing with zero and sign extension.


2005-05-09  Adrian Straetling  <straetling@de.ibm.com>

	* config/s390/s390.md: ("hc"): New mode attribute.
	("extendhidi2", "extendqidi2"): Merge.
	("*extendhidi2", "*extendqidi2"): Merge.
	("extendhisi2", "extendqisi2"): Merge.
	("zero_extendhidi2", "zero_extendqidi2"): Merge.
	("*zero_extendhidi2", "*zero_extendqidi2"): Merge.
	Merged 2 define_split.
	("*zero_extendhisi2", "*zero_extendqisi2"): Merge.
	("*zero_extendhisi2_64", "*zero_extendqisi2_64"): Merge.


Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig	2005-05-04 18:15:14.491486453 +0200
--- gcc/config/s390/s390.md	2005-05-04 18:15:21.501486453 +0200
***************
*** 264,269 ****
--- 264,273 ----
  ;; of a SImode register.
  (define_mode_attr icm_lo [(HI "3") (QI "1")])
  
+ ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
+ ;; HImode and "llgc" in QImode.
+ (define_mode_attr hc [(HI "h") (QI "c")])
+ 
  ;; Maximum unsigned integer that fits in MODE.
  (define_mode_attr max_uint [(HI "65535") (QI "255")])
  
***************
*** 2366,2392 ****
    [(set_attr "op_type" "RRE,RXY")])
  
  ;
! ; extendhidi2 instruction pattern(s).
  ;
  
! (define_expand "extendhidi2"
    [(set (match_operand:DI 0 "register_operand" "")
!         (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
    ""
    "
  {
    if (!TARGET_64BIT)
      {
        rtx tmp = gen_reg_rtx (SImode);
!       emit_insn (gen_extendhisi2 (tmp, operands[1]));
        emit_insn (gen_extendsidi2 (operands[0], tmp));
        DONE;
      }
    else
      {
        operands[1] = gen_lowpart (DImode, operands[1]);
!       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
!       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
        DONE;
      }
  }
--- 2370,2398 ----
    [(set_attr "op_type" "RRE,RXY")])
  
  ;
! ; extend(hi|qi)di2 instruction pattern(s).
  ;
  
! (define_expand "extend<mode>di2"
    [(set (match_operand:DI 0 "register_operand" "")
!         (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
    ""
    "
  {
    if (!TARGET_64BIT)
      {
        rtx tmp = gen_reg_rtx (SImode);
!       emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
        emit_insn (gen_extendsidi2 (operands[0], tmp));
        DONE;
      }
    else
      {
+       rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - 
+ 			      GET_MODE_BITSIZE (<MODE>mode));
        operands[1] = gen_lowpart (DImode, operands[1]);
!       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
!       emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
        DONE;
      }
  }
***************
*** 2399,2431 ****
    "lgh\t%0,%1"
    [(set_attr "op_type" "RXY")])
  
- ;
- ; extendqidi2 instruction pattern(s).
- ;
- 
- (define_expand "extendqidi2"
-   [(set (match_operand:DI 0 "register_operand" "")
-         (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
-   ""
-   "
- {
-   if (!TARGET_64BIT)
-     {
-       rtx tmp = gen_reg_rtx (SImode);
-       emit_insn (gen_extendqisi2 (tmp, operands[1]));
-       emit_insn (gen_extendsidi2 (operands[0], tmp));
-       DONE;
-     }
-   else
-     {
-       operands[1] = gen_lowpart (DImode, operands[1]);
-       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
-       emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
-       DONE;
-     }
- }
- ")
- 
  (define_insn "*extendqidi2"
    [(set (match_operand:DI 0 "register_operand" "=d")
          (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
--- 2405,2410 ----
***************
*** 2449,2466 ****
    "")
  
  ;
! ; extendhisi2 instruction pattern(s).
  ;
  
! (define_expand "extendhisi2"
    [(set (match_operand:SI 0 "register_operand" "")
!         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
    ""
    "
  {
    operands[1] = gen_lowpart (SImode, operands[1]);
!   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
!   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
    DONE;
  }
  ")
--- 2428,2447 ----
    "")
  
  ;
! ; extend(hi|qi)si2 instruction pattern(s).
  ;
  
! (define_expand "extend<mode>si2"
    [(set (match_operand:SI 0 "register_operand" "")
!         (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
    ""
    "
  {
+   rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - 
+ 			  GET_MODE_BITSIZE(<MODE>mode));
    operands[1] = gen_lowpart (SImode, operands[1]);
!   emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
!   emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
    DONE;
  }
  ")
***************
*** 2474,2496 ****
     lhy\t%0,%1"
    [(set_attr "op_type" "RX,RXY")])
  
- ;
- ; extendqisi2 instruction pattern(s).
- ;
- 
- (define_expand "extendqisi2"
-   [(set (match_operand:SI 0 "register_operand" "")
-         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
-   ""
-   "
- {
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
-   emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
-   DONE;
- }
- ")
- 
  (define_insn "*extendqisi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
          (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
--- 2455,2460 ----
***************
*** 2548,2584 ****
    [(set_attr "op_type" "RRE,RXY")])
  
  ;
! ; zero_extendhidi2 instruction pattern(s).
  ;
  
! (define_expand "zero_extendhidi2"
    [(set (match_operand:DI 0 "register_operand" "")
!         (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
    ""
    "
  {
    if (!TARGET_64BIT)
      {
        rtx tmp = gen_reg_rtx (SImode);
!       emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
        emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
        DONE;
      }
    else
      {
        operands[1] = gen_lowpart (DImode, operands[1]);
!       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
!       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
        DONE;
      }
  }
  ")
  
! (define_insn "*zero_extendhidi2"
    [(set (match_operand:DI 0 "register_operand" "=d")
!         (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
    "TARGET_64BIT"
!   "llgh\t%0,%1"
    [(set_attr "op_type" "RXY")])
  
  ;
--- 2512,2550 ----
    [(set_attr "op_type" "RRE,RXY")])
  
  ;
! ; zero_extend(hi|qi)di2 instruction pattern(s).
  ;
  
! (define_expand "zero_extend<mode>di2"
    [(set (match_operand:DI 0 "register_operand" "")
!         (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
    ""
    "
  {
    if (!TARGET_64BIT)
      {
        rtx tmp = gen_reg_rtx (SImode);
!       emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
        emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
        DONE;
      }
    else
      {
+       rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - 
+ 			      GET_MODE_BITSIZE(<MODE>mode));
        operands[1] = gen_lowpart (DImode, operands[1]);
!       emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
!       emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
        DONE;
      }
  }
  ")
  
! (define_insn "*zero_extend<mode>di2"
    [(set (match_operand:DI 0 "register_operand" "=d")
!         (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
    "TARGET_64BIT"
!   "llg<hc>\t%0,%1"
    [(set_attr "op_type" "RXY")])
  
  ;
***************
*** 2616,2632 ****
     llgt\t%0,%1"
    [(set_attr "op_type"  "RRE,RXE")])
  
- (define_split
-   [(set (match_operand:SI 0 "register_operand" "")
-         (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
- 		(const_int 2147483647)))
-    (clobber (reg:CC 33))]
-   "TARGET_64BIT && reload_completed"
-   [(set (match_dup 0)
-         (and:SI (match_dup 1)
- 		(const_int 2147483647)))]
-   "")
- 
  (define_insn "*llgt_didi"
    [(set (match_operand:DI 0 "register_operand" "=d,d")
          (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
--- 2582,2587 ----
***************
*** 2638,2708 ****
    [(set_attr "op_type"  "RRE,RXE")])
  
  (define_split
!   [(set (match_operand:DI 0 "register_operand" "")
!         (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
!                 (const_int 2147483647)))
     (clobber (reg:CC 33))]
    "TARGET_64BIT && reload_completed"
    [(set (match_dup 0)
!         (and:DI (match_dup 1)
!                 (const_int 2147483647)))]
    "")
  
  ;
! ; zero_extendqidi2 instruction pattern(s)
! ;
! 
! (define_expand "zero_extendqidi2"
!   [(set (match_operand:DI 0 "register_operand" "")
!         (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
!   ""
!   "
! {
!   if (!TARGET_64BIT)
!     {
!       rtx tmp = gen_reg_rtx (SImode);
!       emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
!       emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
!       DONE;
!     }
!   else
!     {
!       operands[1] = gen_lowpart (DImode, operands[1]);
!       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
!       emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
!       DONE;
!     }
! }
! ")
! 
! (define_insn "*zero_extendqidi2"
!   [(set (match_operand:DI 0 "register_operand" "=d")
!         (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
!   "TARGET_64BIT"
!   "llgc\t%0,%1"
!   [(set_attr "op_type" "RXY")])
! 
! ;
! ; zero_extendhisi2 instruction pattern(s).
  ;
  
! (define_expand "zero_extendhisi2"
    [(set (match_operand:SI 0 "register_operand" "")
!         (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
    ""
    "
  {
    operands[1] = gen_lowpart (SImode, operands[1]);
!   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
    DONE;
  }
  ")
  
! (define_insn "*zero_extendhisi2_64"
    [(set (match_operand:SI 0 "register_operand" "=d")
!         (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
    "TARGET_ZARCH"
!   "llgh\t%0,%1"
    [(set_attr "op_type" "RXY")])
  
  (define_insn_and_split "*zero_extendhisi2_31"
--- 2593,2630 ----
    [(set_attr "op_type"  "RRE,RXE")])
  
  (define_split
!   [(set (match_operand:GPR 0 "register_operand" "")
!         (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
!                  (const_int 2147483647)))
     (clobber (reg:CC 33))]
    "TARGET_64BIT && reload_completed"
    [(set (match_dup 0)
!         (and:GPR (match_dup 1)
!                  (const_int 2147483647)))]
    "")
  
  ;
! ; zero_extend(hi|qi)si2 instruction pattern(s).
  ;
  
! (define_expand "zero_extend<mode>si2"
    [(set (match_operand:SI 0 "register_operand" "")
!         (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
    ""
    "
  {
    operands[1] = gen_lowpart (SImode, operands[1]);
!   emit_insn (gen_andsi3 (operands[0], operands[1], 
!     GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
    DONE;
  }
  ")
  
! (define_insn "*zero_extend<mode>si2_64"
    [(set (match_operand:SI 0 "register_operand" "=d")
!         (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
    "TARGET_ZARCH"
!   "llg<hc>\t%0,%1"
    [(set_attr "op_type" "RXY")])
  
  (define_insn_and_split "*zero_extendhisi2_31"
***************
*** 2718,2746 ****
       (clobber (reg:CC 33))])]
    "operands[2] = gen_lowpart (HImode, operands[0]);")
  
- ;
- ; zero_extendqisi2 instruction pattern(s).
- ;
- 
- (define_expand "zero_extendqisi2"
-   [(set (match_operand:SI 0 "register_operand" "")
-         (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
-   ""
-   "
- {
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
-   DONE;
- }
- ")
- 
- (define_insn "*zero_extendqisi2_64"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-   "TARGET_ZARCH"
-   "llgc\t%0,%1"
-   [(set_attr "op_type" "RXY")])
- 
  (define_insn_and_split "*zero_extendqisi2_31"
    [(set (match_operand:SI 0 "register_operand" "=&d")
          (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
--- 2640,2645 ----


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