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Re: PR target/21416: Fix MIPS __builtin_isless{,equal}


Richard Sandiford <rsandifo@redhat.com> writes:
> Tested on mips64-elf and applied to mainline.  I think this is
> is a regression from 2.95, so I'll apply it to 4.0 as well after
> testing has finished.  3.4 predates the macro stuff and will need
> a slightly different patch.

Here's the 3.4 version, which I committed after testing on mips64-elf.

Also, I changed the testcases to use dg-mips-options instead of
dg-options, which means we'll skip them when doing -msoft-float
multilib tests.  I didn't apply the testcases to either branch
because the dg-mips-options stuff is only in mainline.

FWIW, I ran the installed 3.4 and 4.0 compilers against the mainline
gcc.target/mips to check that the new tests do indeed pass.

Richard


	PR target/21416
	* config/mips/mips.c (mips_emit_compare): Don't reverse UNGE and UNGT
	comparisons.
	* config/mips/mips.md (sungt_df, sunge_df, sungt_sf, sunge_sf): New
	patterns.

Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.362.4.16
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.362.4.16 mips.c
--- config/mips/mips.c	7 Jul 2004 19:21:10 -0000	1.362.4.16
+++ config/mips/mips.c	8 May 2005 11:59:40 -0000
@@ -3049,8 +3049,6 @@ get_float_compare_codes (enum rtx_code i
   switch (in_code)
     {
     case NE:
-    case UNGE:
-    case UNGT:
     case LTGT:
     case ORDERED:
       *cmp_code = reverse_condition_maybe_unordered (in_code);
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.211.4.10
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.211.4.10 mips.md
--- config/mips/mips.md	7 Oct 2004 06:38:44 -0000	1.211.4.10
+++ config/mips/mips.md	8 May 2005 11:59:41 -0000
@@ -7765,6 +7765,24 @@ (define_insn "sunle_df"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
 
+(define_insn "sungt_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(ungt:CC (match_operand:DF 1 "register_operand" "f")
+	         (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "c.ult.d\t%Z0%2,%1"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
+
+(define_insn "sunge_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(unge:CC (match_operand:DF 1 "register_operand" "f")
+	         (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "c.ule.d\t%Z0%2,%1"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
+
 (define_insn "seq_df"
   [(set (match_operand:CC 0 "register_operand" "=z")
 	(eq:CC (match_operand:DF 1 "register_operand" "f")
@@ -7846,6 +7864,24 @@ (define_insn "sunle_sf"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
 
+(define_insn "sungt_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(ungt:CC (match_operand:SF 1 "register_operand" "f")
+	         (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "c.ult.s\t%Z0%2,%1"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
+
+(define_insn "sunge_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(unge:CC (match_operand:SF 1 "register_operand" "f")
+	         (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "c.ule.s\t%Z0%2,%1"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "FPSW")])
+
 (define_insn "seq_sf"
   [(set (match_operand:CC 0 "register_operand" "=z")
 	(eq:CC (match_operand:SF 1 "register_operand" "f")


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