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RE: [rfc] multi-word subreg lowering pass



Richard Henderson wrote:
If the target leaves logical arithmetic to the middle end, this
means that the posted example,
	long long foo(int x, long long y) {
	  return x & y;
	}

will decompose to

	(set (reg:SI 100) (reg:SI x))
	(set (reg:SI 101) (const_int 0))
	(set (reg:SI 102) (and:SI (reg:SI 100) (reg:SI ylow)))
	(set (reg:SI 103) (and:SI (reg:SI 101) (reg:SI yhigh)))
	(set (reg:SI eax) (reg:SI 102))
	(set (reg:SI edx) (reg:SI 103))

Are you sure? This isn't correct. The input value is sign extended. LLVM produces this:


foo:
        movl 4(%esp), %eax
        movl %eax, %edx
        sarl $31, %edx
        andl 12(%esp), %edx
        andl 8(%esp), %eax
        ret

I don't think there is any way to get rid of the sar or the second and for this example. If the first arg is changed to unsigned, I get this:

foo:
        movl 8(%esp), %eax
        andl 4(%esp), %eax
        movl $0, %edx
        ret

Is this the case you mean?

-Chris

--
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/


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