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This patch adds support for the MIPS 24K processor family.
The new attrib "cnv_mode" is introduced to catch the different float/int
conversions, which have different delays.
David.
2005-05-04 David Ung <davidu@mips.com>
* config/mips/mips.h (processor_type): Add names for the 24K.
(TARGET_MIPS24K, TARGET_MIPS24KX): New defs.
(TUNE_MIPS24K, TUNE_MIPS24KX): Similarly.
* config/mips/mips.c (mips_cpu_info_table): Add names for the 24K
processor family.
* config/mips/mips.md (cnv_mode): New attribute for recording the
conversion types of fcvt/xfer insns.
(cpu): Add 24k and 24kx.
(include): Include 24k.md file.
("truncdfsf2", "extendsfdf2", "fix_truncdfsi2_insn")
("fix_truncdfsi2_macro", "fix_truncsfsi2_insn")
("fix_truncsfsi2_macro", "fix_truncdfdi2", "fix_truncsfdi2")
("floatsidf2", "floatdidf2", "floatsisf2", "floatdisf2")
("*movdi_64bit", "*movsi_internal", "movcc", "*movhi_internal")
("*movqi_internal", "*movsf_hardfloat")
("*movdf_hardfloat_64bit", "*movdf_hardfloat_32bit")
("*movdf_softfloat", "load_df_low", "load_df_high")
("store_df_high", "store_df_high"): Setup cnv_mode.
* config/mips/24k.md: New file, contains 24k DFA pipeline
description.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.c,v
retrieving revision 1.498
diff -c -3 -p -r1.498 mips.c
*** config/mips/mips.c 26 Apr 2005 17:55:23 -0000 1.498
--- config/mips/mips.c 4 May 2005 11:12:39 -0000
*************** const struct mips_cpu_info mips_cpu_info
*** 700,705 ****
--- 700,709 ----
/* MIPS32 Release 2 */
{ "m4k", PROCESSOR_M4K, 33 },
+ { "24k", PROCESSOR_24K, 33 },
+ { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
+ { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
+ { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.h,v
retrieving revision 1.390
diff -c -3 -p -r1.390 mips.h
*** config/mips/mips.h 27 Apr 2005 09:11:58 -0000 1.390
--- config/mips/mips.h 4 May 2005 11:12:39 -0000
*************** enum processor_type {
*** 36,41 ****
--- 36,43 ----
PROCESSOR_4KC,
PROCESSOR_5KC,
PROCESSOR_20KC,
+ PROCESSOR_24K,
+ PROCESSOR_24KX,
PROCESSOR_M4K,
PROCESSOR_R3000,
PROCESSOR_R3900,
*************** extern const struct mips_cpu_info *mips_
*** 161,166 ****
--- 163,170 ----
#define ISA_MIPS64 (mips_isa == 64)
/* Architecture target defines. */
+ #define TARGET_MIPS24K (mips_arch == PROCESSOR_24K)
+ #define TARGET_MIPS24KX (mips_arch == PROCESSOR_24KX)
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
*************** extern const struct mips_cpu_info *mips_
*** 173,178 ****
--- 177,184 ----
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
/* Scheduling target defines. */
+ #define TUNE_MIPS24K (mips_tune == PROCESSOR_24K)
+ #define TUNE_MIPS24KX (mips_tune == PROCESSOR_24KX)
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mips/mips.md,v
retrieving revision 1.315
diff -c -3 -p -r1.315 mips.md
*** config/mips/mips.md 13 Mar 2005 18:03:25 -0000 1.315
--- config/mips/mips.md 4 May 2005 11:12:40 -0000
***************
*** 157,162 ****
--- 157,172 ----
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
(const_string "unknown"))
+ ;; Mode for conversion types (fcvt and xfer)
+ ;; I2S integer to float single (SI/DI to SF)
+ ;; I2D integer to float double (SI/DI to DF)
+ ;; F2I float to integer (SF/DF to SI/DI)
+ ;; D2S double to float single
+ ;; S2D float single to double
+
+ (define_attr "cnv_mode" "unknown,I2S,I2D,F2I,D2S,S2D"
+ (const_string "unknown"))
+
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(const_string "no"))
***************
*** 254,260 ****
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
! "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
--- 264,270 ----
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
! "default,4kc,5kc,20kc,24k,24kx,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
***************
*** 478,483 ****
--- 488,494 ----
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
+ (include "24k.md")
(include "3000.md")
(include "4000.md")
(include "4100.md")
*************** beq\t%2,%.,1b\;\
*** 2130,2135 ****
--- 2141,2147 ----
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.s.d\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "D2S")
(set_attr "mode" "SF")])
;; Integer truncation patterns. Truncating SImode values to smaller
*************** beq\t%2,%.,1b\;\
*** 2444,2449 ****
--- 2456,2462 ----
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.d.s\t%0,%1"
[(set_attr "type" "fcvt")
+ (set_attr "cnv_mode" "S2D")
(set_attr "mode" "DF")])
;;
*************** beq\t%2,%.,1b\;\
*** 2472,2477 ****
--- 2485,2491 ----
"trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "4")])
(define_insn "fix_truncdfsi2_macro"
*************** beq\t%2,%.,1b\;\
*** 2487,2492 ****
--- 2501,2507 ----
}
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "36")])
(define_expand "fix_truncsfsi2"
*************** beq\t%2,%.,1b\;\
*** 2508,2513 ****
--- 2523,2529 ----
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "4")])
(define_insn "fix_truncsfsi2_macro"
*************** beq\t%2,%.,1b\;\
*** 2523,2528 ****
--- 2539,2545 ----
}
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "36")])
*************** beq\t%2,%.,1b\;\
*** 2533,2538 ****
--- 2550,2556 ----
"trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 2543,2548 ****
--- 2561,2567 ----
"trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "F2I")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 2553,2558 ****
--- 2572,2578 ----
"cvt.d.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 2563,2568 ****
--- 2583,2589 ----
"cvt.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "I2D")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 2573,2578 ****
--- 2594,2600 ----
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 2583,2588 ****
--- 2605,2611 ----
"cvt.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "I2S")
(set_attr "length" "4")])
*************** beq\t%2,%.,1b\;\
*** 3111,3116 ****
--- 3134,3140 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
(set_attr "mode" "DI")
+ (set_attr "cnv_mode" "*,*,*,*,*,*,I2D,*,F2I,*,*,*,*,*,*")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
(define_insn "*movdi_64bit_mips16"
*************** beq\t%2,%.,1b\;\
*** 3207,3212 ****
--- 3231,3237 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,xfer,load,xfer,store")
(set_attr "mode" "SI")
+ (set_attr "cnv_mode" "*,*,*,*,*,*,I2S,*,F2I,*,F2I,I2S,*,*,*,*,*")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,*,4,*")])
(define_insn "*movsi_mips16"
*************** beq\t%2,%.,1b\;\
*** 3308,3313 ****
--- 3333,3339 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
(set_attr "mode" "SI")
+ (set_attr "cnv_mode" "*,*,*,*,F2I,I2S,*,*,*")
(set_attr "length" "8,4,*,*,4,4,4,*,*")])
;; Reload condition code registers. reload_incc and reload_outcc
*************** beq\t%2,%.,1b\;\
*** 3408,3413 ****
--- 3434,3440 ----
mt%0\t%1"
[(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
(set_attr "mode" "HI")
+ (set_attr "cnv_mode" "*,*,*,*,F2I,I2S,*,*")
(set_attr "length" "4,4,*,*,4,4,4,4")])
(define_insn "*movhi_mips16"
*************** beq\t%2,%.,1b\;\
*** 3515,3520 ****
--- 3542,3548 ----
mt%0\t%1"
[(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
(set_attr "mode" "QI")
+ (set_attr "cnv_mode" "*,*,*,*,F2I,I2S,*,*")
(set_attr "length" "4,4,*,*,4,4,4,4")])
(define_insn "*movqi_mips16"
*************** beq\t%2,%.,1b\;\
*** 3585,3590 ****
--- 3613,3619 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "SF")
+ (set_attr "cnv_mode" "*,I2S,*,*,*,I2S,F2I,*,*,*")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
(define_insn "*movsf_softfloat"
*************** beq\t%2,%.,1b\;\
*** 3630,3635 ****
--- 3659,3665 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "*,I2D,*,*,*,I2D,F2I,*,*,*")
(set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
(define_insn "*movdf_hardfloat_32bit"
*************** beq\t%2,%.,1b\;\
*** 3641,3646 ****
--- 3671,3677 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "*,I2D,*,*,*,I2D,F2I,*,*,*")
(set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
(define_insn "*movdf_softfloat"
*************** beq\t%2,%.,1b\;\
*** 3652,3657 ****
--- 3683,3689 ----
{ return mips_output_move (operands[0], operands[1]); }
[(set_attr "type" "arith,load,store,xfer,xfer,fmove")
(set_attr "mode" "DF")
+ (set_attr "cnv_mode" "*,*,*,F2I,I2D,*")
(set_attr "length" "8,*,*,4,4,4")])
(define_insn "*movdf_mips16"
*************** beq\t%2,%.,1b\;\
*** 3782,3787 ****
--- 3814,3820 ----
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpload")
+ (set_attr "cnv_mode" "I2D,*")
(set_attr "mode" "SF")])
;; Load the high word of operand 0 from operand 1, preserving the value
*************** beq\t%2,%.,1b\;\
*** 3797,3802 ****
--- 3830,3836 ----
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpload")
+ (set_attr "cnv_mode" "I2D,*")
(set_attr "mode" "SF")])
;; Store the high word of operand 1 in operand 0. The corresponding
*************** beq\t%2,%.,1b\;\
*** 3811,3816 ****
--- 3845,3851 ----
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpstore")
+ (set_attr "cnv_mode" "F2I,*")
(set_attr "mode" "SF")])
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
Attachment:
24k.md
Description: application/genesis-rom
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